TUSB5052 datasheet(49/82 Pages) TI

49 / 82 page

7−1

7 UARTs

7.1

UART Registers

Table 7−1 summarizes the UART registers. These registers are used for data I/O, control, and status information.

UART setup is done by the MCU. Data transfer is typically performed by the DMAC. However, the MCU can perform

data transfer without the DMA; this is useful when debugging the firmware.

Table 7−1. UART Register Summary

ACCESS

FUNCTION

COMMENTS

RDR

R/O

UART Receiver data register

Can be accessed by MCU or DMA

TDR

W/O

UART Transmitter data register

Can be accessed by MCU or DMA

LCR

R/W

UART Line control register

FCRL

R/W

UART Flow control register

MCR

R/W

UART Modem control register

LSR

R/O

UART Line status register

Can generate an interrupt

MSR

R/O

UART Modem status register

Can generate an interrupt

DLL

R/W

UART Divisor register (low-byte)

DLH

R/W

UART Divisor register (high-byte)

XON

R/W

UART Xon register

XOFF

R/W

UART Xoff register

MASK

R/W

UART Interrupt mask register

Can control three interrupt sources

7.1.1

RDR[2:1]: Receiver Data Registers (2 Registers)

Each of the two receiver data registers consists of a 32-byte FIFO. Data received from the SIN pin are converted from

serial to parallel format and stored in this FIFO. Data transfer from these resisters to the RAM buffer is the

responsibility of the DMA controller.

R/O

BIT

NAME

RESET

FUNCTION

7−0

D[7:0]

Receiver byte

7.1.2

TDR[2:1]: Transmitter Data Registers (2 Registers)

Each of the two transmitter data registers is double buffered. Data written to these registers are loaded into the

shift-register, and shifted out on SOUT. Data transfer from the RAM buffer to these registers is the responsibility of

the DMA controller.

W/O

BIT

NAME

RESET

FUNCTION

7−0

D[7:0]

Transmitter byte

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