LM97600CIUTSLASHNOPB datasheet(4/58 Pages) TI1

4 / 58 page

GND

RCLK

VCM_CLK

50k

GND

50k

LM97600

SNAS600A – JULY 2012 – REVISED MARCH 2013

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PIN DESCRIPTIONS and EQUIVALENT CIRCUITS

Pin No.

Symbol

Equivalent Circuit

Description

Serial Chip Select (active low)

(Input):LVCMOS This pin functions as the serial interface chip

SCS

select. See USING THE SERIAL INTERFACE for description of the

serial interface.

Serial Interface Clock

(Input):LVCMOS This pin functions as the SCLK input which

SCLK

clocks the serial data. See USING THE SERIAL INTERFACE for

description of the serial interface.

Serial Data In

(Input):LVCMOS This pin functions as the SDATA input. See

SDI

USING THE SERIAL INTERFACE for description of the serial

interface.

Power Down

(Input):LVCMOS A logic high on the PD pin puts the entire device

into the Power Down Mode.

Calibration Cycle Initiate

(Input):LVCMOS A minimum 80 input clock cycles logic low

followed by a minimum of 80 input clock cycles high on this pin

CAL

initiates the calibration sequence. See Calibration for an overview

of self-calibration and On-Command Calibration for a description of

on-command calibration.

Sampling Clock Input

(Input):LVDS The differential clock signal must be a.c. coupled to

CLK+

these pins. The input signal is sampled on both the rising and

CLK

−

falling edge of CLK. See Acquiring the Input for a description of

acquiring the input and THE SAMPLE CLOCK INPUT for an

overview of the clock inputs.

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