Distribution

Path

SYNC*

CLKout0

CLKout1

CLKout2

LMK02002

SNAS418 – AUGUST 2007

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CLKout DELAYS

Each individual clock output includes a delay adjustment. Clock output delay registers (CLKoutX_DLY) support a

150 ps step size and range from 0 to 2250 ps of total delay.

LVPECL OUTPUTS

Each LVPECL output may be disabled individually by programming the CLKoutX_EN bits. All the outputs may be

disabled simultaneously by pulling the GOE pin low or programming EN_CLKout_Global to 0.

GLOBAL CLOCK OUTPUT SYNCHRONIZATION

The SYNC* pin synchronizes the clock outputs. When the SYNC* pin is held in a logic low state, the divided

outputs are also held in a logic low state. When the SYNC* pin goes high, the divided clock outputs are activated

and will transition to a high state simultaneously. Clocks in the bypassed state are not affected by SYNC* and

are always synchronized with the divided outputs.

The SYNC* pin must be held low for greater than one clock cycle of the Frequency Input port, also known as the

distribution path. Once this low event has been registered, the outputs will not reflect the low state for four more

cycles. Similarly once the SYNC* pin becomes high, the outputs will not simultaneously transition high until four

more distribution path clock cycles have passed. See the timing diagram below for further detail. In the timing

diagram below the clocks are programmed as CLKout0_MUX = Bypassed, CLKout1_MUX = Divided,

CLKout1_DIV = 2, CLKout2_MUX = Divided, and CLKout2_DIV = 4.

SYNC* Timing Diagram

The SYNC* pin provides an internal pull-up resistor as shown on the functional block diagram. If the SYNC* pin

is not terminated externally the clock outputs will operate normally. If the SYNC* function is not used, clock

output synchronization is not specified.

CLKout OUTPUT STATES

Each clock output may be individually enabled with the CLKoutX_EN bits. Each individual output enable control

bit is gated with the Global Output Enable input pin (GOE) and the Global Output Enable bit

(EN_CLKout_Global).

All clock outputs can be disabled simultaneously if the GOE pin is pulled low by an external signal or

EN_CLKout_Global is set to 0.

CLKoutX

EN_CLKout

GOE pin

Clock X Output State

_EN bit

_Global bit

1

1

Low

Low

Don't care

0

Don't care

Off

0

Don't care

Don't care

Off

1

1

High / No Connect

Enabled

8

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