LMK02002

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SNAS418 – AUGUST 2007

DIV4

Digital Lock Detect Circuitry Mode

0

Not divided; Phase detector frequency

≤ 20 MHz (default)

1

Divided by 4; Phase detector frequency > 20 MHz

REGISTER R14

The LMK02002 requires register R14 to be programmed as shown in the register map (see Table 1).

PLL_R[11:0] -- R Divider Value

These bits program the PLL R Divider and are programmed in binary fashion.

PLL_R[11:0]

PLL R Divide Value

0

0

0

0

0

0

0

0

0

0

0

0

Invalid

0

0

0

0

0

0

0

0

0

0

0

1

1

0

0

0

0

0

0

0

0

0

0

1

0

2

.

.

.

.

.

.

.

.

.

.

.

.

...

0

0

0

0

0

0

0

0

1

0

1

0

10 (default)

.

.

.

.

.

.

.

.

.

.

.

.

...

1

1

1

1

1

1

1

1

1

1

1

1

4095

PLL_MUX[3:0] -- Multiplexer Control for LD Pin

These bits set the output mode of the LD pin. The table below lists several different modes.

PLL_MUX[3:0]

Output Type

LD Pin Function

0

Hi-Z

Disabled (default)

1

Push-Pull

Logic High

2

Push-Pull

Logic Low

3

Push-Pull

Digital Lock Detect (Active High)

4

Push-Pull

Digital Lock Detect (Active Low)

5

Push-Pull

Analog Lock Detect

6

Open Drain NMOS

Analog Lock Detect

7

Open Drain PMOS

Analog Lock Detect

8

Invalid

9

Push-Pull

N Divider Output/2 (50% Duty Cycle)

10

Invalid

11

Push-Pull

R Divider Output/2 (50% Duty Cycle)

12 to 15

Invalid

POWERDOWN bit -- Device Power Down

This bit can power down the device. Enabling this bit powers down the entire device and all blocks, regardless of

the state of any of the other bits or pins.

POWERDOWN bit

Mode

0

Normal Operation (default)

1

Entire Device Powered Down

EN_CLKout_Global bit -- Global Clock Output Enable

This bit overrides the individual CLKoutX_EN bits (See CLKoutX_EN bit -- Clock Output Enables). When this bit

is set to 0, all clock outputs are disabled, regardless of the state of any of the other bits or pins. See CLKout

OUTPUT STATES for more information on CLKout states.

Copyright © 2007, Texas Instruments Incorporated

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