TAS3108IADCPRG4 datasheet(5/63 Pages) TI1

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2.7 Audio DSP Core

TAS3108, TAS3108IA

AUDIO DIGITAL SIGNAL PROCESSORS

SLES152B – OCTOBER 2005 – REVISED NOVEMBER 2007

The audio DSP core arithmetic unit is a fixed-point computational engine consisting of an arithmetic unit

and data and coefficient memory blocks. The primary features of the audio DSP core are:

• 48-bit data path with 76-bit accumulator

• Hardware multiplier (28 bit × 48bit)

• Read/write single-cycle memory access

• Input is 48-bit 2s-complement data multiplexed in from the SAP immediately following an LRCLK pulse.

• Output is 32-bit 2s-complement data on four buses.

• Separate control for writing to delay memory

• Separate coefficient memory (28 bit) and data memory (48 bit)

• Linear feedback shift register (LFSR) is a random-number generator that can be used to dither the

audio.

• Coefficient RAM, data RAM, LFSR seed, program counter, and memory pointers are all mapped into

the same 5.88K memory space for convenient addressing by the microprocessor.

• Memory interface block contains four pointers – two for data memory and two for coefficient memory.

The audio DSP core is used to implement all audio processing functions.

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Functional Description

Not Recommended for New Designs

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