TFP403

TI

PanelBus™ DIGITAL RECEIVER

SLDS125B − DECEMBER 2000 − REVISED MAY 2011

9

POST OFFICE BOX 655303

PARAMETER MEASUREMENT INFORMATION

80%

20%

80%

20%

ODCK

Figure 1. Rise and Fall Time of ODCK

80%

80%

20%

20%

QE(0-23), QO(0-23), DE

CTL(1-2), HSYNC, VSYNC

Figure 2. Rise and Fall Time of Data and Control Signals

ODCK

Figure 3. ODCK Frequency

ODCK

QE(0-23), QO(0-23), DE

CTL(1-2), HSYNC, VSYNC

OCK_INV

Figure 4. Data Setup and Hold Time to Rising and Falling Edge of ODCK

Figure 5. ODCK High to QE[23:0]

Staggered Data Output

Figure 6. Analog Input Intra-Pair

Differential Skew

50%

ODCK

QE(O-23)

50%

Tx+

Tx-