TFP403

TI

PanelBus™ DIGITAL RECEIVER

SLDS125B − DECEMBER 2000 − REVISED MAY 2011

10

POST OFFICE BOX 655303

PARAMETER MEASUREMENT INFORMATION

Figure 7. Delay From PD Low to Hi-Z Outputs

Figure 8. Delay From PDO Low to Hi-Z Outputs

PD

QE(0-23), QO(0-23),

ODCK, DE, CTL(1-2),

HSYNC, VSYNC, SCDT

PDO

QE(0-23), QO(0-23),

ODCK, DE, CTL2,

HSYNC, VSYNC

Figure 9. Analog Input Channel-to-Channel Skew

50%

50%

TX2

TX1

TX0

DE

SCDT

Figure 10. Time Between DE Transitions to SCDT Low and SCDT High

DE

Figure 11. Minimum DE Low and Maximum DE High