TFP501

www.ti.com

SLDS127C

– JULY 2001 – REVISED JULY 2011

Bit 6: REPEATER, Video repeater capability. This device is not a repeater. Read as ZERO.

Bit 5: READY, KSV FIFO ready. This device does not support repeater capability. Read as ZERO.

Bit 4: FAST. This device supports 400 kHz transfers. Read as ONE.

Bstatus

Subaddress = 41

Read Only

Default = 00

7

6

5

4

3

2

1

0

Bstatus[7:0]

Subaddress = 42

Read Only

Default = 00

7

6

5

4

3

2

1

0

Bstatus[15:8]

Bstatus. This device does not support repeater capability. All bytes read as 0x00.

KSV_FIFO

Subaddress = 43

Read Only

Default = 00

7

6

5

4

3

2

1

0

KSV_FIFO

Key selection vector FIFO. This device is not a repeater. All bytes read as 0x00.

VEN_ID

Subaddress = C0

Read Only

Default = 4C

7

6

5

4

3

2

1

0

VEN_ID[7:0]

Subaddress = C1

Read Only

Default = 01

7

6

5

4

3

2

1

0

VEN_ID[15:8]

This read-only register contains the 16-bit Texas Instruments vendor ID for the TFP501. VEN_ID[15:0] is

hardwired to 0x014C

DEV_ID

Subaddress = C2

Read Only

Default = 01

7

6

5

4

3

2

1

0

DEV_ID[7:0]

Subaddress = C3

Read Only

Default = 05

7

6

5

4

3

2

1

0

DEV_ID[15:8]

This read-only register contains the 16-bit device ID for the TFP501. DEV_ID[15:0] is hardwired to 0x0501.

REV_ID

Subaddress = C4

Read Only

Default = 01

7

6

5

4

3

2

1

0

REV_ID[7:0]

This read-only register contains the 8-bit revision ID for the TFP501. REV_ID[7:0] is hardwired to 0x01.

I

line, DDC_SCL, and one serial data line, DDC_SDA. The basic I2C access cycles are shown in Figure 16 and

Figure 17.

Copyright

© 2001–2011, Texas Instruments Incorporated

17