LP2996AMRESLASHNOPB datasheet(17/29 Pages) TI1

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VTT

LP2996

PVIN

VDDQ

VREF

AVIN

VREF = 0.75V

VSENSE

GND

VDDQ = 1.5V

VDD = 2.5V

VTT = 0.75V

CIN

COUT

CREF

LP2996A

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SNOSCY7 – JUNE 2014

Typical Application (continued)

8.2.6 HSTL Applications

The LP2996A can be easily adapted for HSTL applications by connecting VDDQ to the 1.5 V rail. This will produce

a VTT and VREF voltage of approximately 0.75 V for the termination resistors. AVIN and PVIN should be

connected to a 2.5 V rail for optimal performance.

Figure 28. HSTL Application

8.2.7 QDR Applications

Quad data rate (QDR) applications utilize multiple channels for improved memory performance. However, this

increase in bus lines has the effect of increasing the current levels required for termination. The recommended

approach in terminating multiple channels is to use a dedicated LP2996A for each channel. This simplifies layout

and reduces the internal power dissipation for each regulator. Separate VREF signals can be used for each DIMM

bank from the corresponding regulator with the chipset reference provided by a local resistor divider or one of the

LP2996A signals. Because VREF and VTT are expected to track and the part to part variations are minor, there

should be little difference between the reference signals of each LP2996A.

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LP2996AMRE/NOPB 데이터시트(PDF) 17 Page - Texas Instruments