LP3470 datasheet(8/22 Pages) TI1

8 / 22 page

LP3470

REF

DELAY

GND

Reset

SRT

CC1

LP3470

SNVS003G – JUNE 1999 – REVISED APRIL 2016

www.ti.com

Product Folder Links: LP3470

Submit Documentation Feedback

7 Detailed Description

7.1 Overview

The LP3470 micropower voltage supervisory circuit provides a simple solution to monitor the power supplies in

microprocessor and digital systems and provides a reset controlled by the factory-programmed reset threshold

on the VCC supply voltage pin. When the voltage declines below the reset threshold, the reset signal is asserted

and remains asserted for an interval programmed by an external capacitor after VCC has risen above the

threshold voltage. The reset threshold options are 2.63 V, 2.93 V, 3.08 V, 3.65 V, 4 V, 4.38 V, 4.63 V.

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 Reset Time-Out Period

The reset time-out period (tRP) is programmable using an external capacitor (C1) connected to pin SRT of

LP3470. A ceramic chip capacitor rated at or above 10 V is sufficient. The reset time-out period (tRP) can be

calculated using Equation 1.

tRP (ms) = 2000 x C1 (µF)

(1)

For example a C1 of 100 nF will achieve a tRP of 200 ms. If no delay due to tRP is needed in a certain application,

the pin SRT must be left floating.

7.3.2 Reset Output

In applications like microprocessor (µP) systems, errors might occur in system operation during power up, power

down, or brownout conditions. It is imperative to monitor the power supply voltage to prevent these errors from

occurring.

The LP3470 asserts a reset signal whenever the VCC supply voltage is below a threshold (VRTH) voltage. Reset is

ensured to be a logic low for VCC > 0.5 V. Once VCC exceeds the reset threshold, the reset is kept asserted for a

time period (tRP) programmed by an external capacitor (C1); after this interval Reset goes to logic high. If a

brownout condition occurs (monitored voltage falls below the reset threshold minus a small hysteresis), Reset

goes low. When VCC returns above the reset threshold, Reset remains low for a time period tRP before going to

logic high. Figure 9 shows this behavior.

LP3470 데이터시트(PDF) 8 Page - Texas Instruments