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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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CS8414 데이터시트(PDF) 13 Page - List of Unclassifed Manufacturers |
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CS8414 데이터시트(HTML) 13 Page - List of Unclassifed Manufacturers |
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13 / 38 page  CS8413 CS8414 DS240F1 13 and output random data if ROER is not set. The conditions that activate ERF are those reported in SR2 and enabled in IER2. Figure 10 illustrates the modes selectable by SDF2-SDF0 and FSF1-FSF0. MSTR, which in most applications will be set to one, determines whether FSYNC and SCK are out- puts (MSTR = 1) or inputs (MSTR = 0). When FSYNC and SCK are inputs (slave mode) the audio data can be read twice or missed if the device con- trolling FSYNC and SCK is on a different time- base than the CS8413. If the audio data is read twice or missed, the SLIP bit in SR1 is set. SCED selects the SCK edge to output data on. SCED high causes data to be output on the falling edge, and SCED low causes data to be output on the rising edge. 24 Bits, Incl. Aux 16 Clocks 16 Clocks 16 Clocks 16 Clocks 32 Clocks 32 Clocks 32 Clocks 32 Clocks 00 01 10 11 1 1 1 1 FSYNC Output FSYNC Output FSYNC Output FSYNC Output FSF 00 01 10 11 MSTR 0 0 0 0 FSYNC Input FSYNC Input FSYNC Input FSYNC Input 10 (bit) 000 MSB First - 32 001 011 101 111 MSB Last LSB Last - 16 LSB Last - 18 LSB Last - 20 210 (bit) Name SDF 20 Bits LSB MSB LSB MSB LSB LSB LSB MSB LSB MSB LSB LSB MSB LSB MSB MSB LSB MSB LSB MSB 16 Bits 18 Bits 20 Bits 18 Bits 16 Bits MSB LSB MSB LSB MSB Left Sample Right Sample 32 Bits 32 Bits SPECIAL MODES: * Error flags are not accurate in these modes † FSYNC is inverted FSF = 11 MSB LSB MSB LSB MSB 16 Bits 16 Bits MSB MSB MSB LSB LSB MSB MSB MSB LSB LSB Bi-Phase Mark Data Bi-Phase Mark Data 32 Bits 32 Bits LSB VUCP MSB AUX LSB AUX VUCP MSB AUX 210 MSTR Name SDF 110 0 MSB First - 24 010 0 MSB First - 16 010*† 1 NRZ Data 100* 1 Bi-Phase Data 100 Async SCK 0 24 Bits, Incl. Aux 24 Bits, Incl. Aux 24 Bits, Incl. Aux 24 Bits, Incl. Aux 24 Bits, Incl. Aux 24 Bits, Incl. Aux 24 Bits, Incl. Aux Figure 10. CS8413 Serial Port SDATA and FSYNC Timing |
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