TIME (2 Ps/DIV)

5

4

3

2

1

0

TIME (2 Ps/DIV)

5

4

3

2

1

0

LPV7215

www.ti.com

SNOSAI6I – SEPTEMBER 2005 – REVISED APRIL 2013

Figure 32. Output Signal without Capacitive Load

The plot in Figure 33 shows the output signal when a 20 pF capacitor is added as a load. The step is at about

2.5V.

Figure 33. Output Signal with 20 pF Load

CAPACITIVE AND RESISTIVE LOADS

The propagation delay is not affected by capacitive loads at the output of the LPV7215Q. However, resistive

loads slightly affect the propagation delay on the falling edge by a reduction of almost 2 µs depending on the

load resistance value.

NOISE

Most comparators have rather low gain. This allows the output to spend time between high and low when the

input signal changes slowly. The result is that the output may oscillate between high and low when the

differential input is near zero. The exceptionally high gain of this comparator, 120 dB, eliminates this problem.

Less than 1 µV of change on the input will drive the output from one rail to the other rail. If the input signal is

noisy, the output cannot ignore the noise unless some hysteresis is provided by positive feedback. (See section

on adding hysteresis.)

LAYOUT/BYPASS CAPACITORS

Proper grounding and the use of a ground plane will help to ensure the specified performance of the LPV7215Q.

Minimizing trace lengths, reducing unwanted parasitic capacitance and using surface-mount components will also

help.

Comparators are very sensitive to input noise. To minimize supply noise, power supplies should be capacitively

decoupled by a 0.01 µF ceramic capacitor in parallel with a 10 µF electrolytic capacitor.

HYSTERESIS

In order to improve propagation delay when low overdrive is needed hysteresis can be added.

Copyright © 2005–2013, Texas Instruments Incorporated

Submit Documentation Feedback

13

Product Folder Links: LPV7215