TDA8024AT datasheet(21/29 Pages) PHILIPS

21 / 29 page

2004 July 12

Philips Semiconductors

Product speciﬁcation

IC card interface

TDA8024

fall time

CL = 30 pF; note 5

−−

duty factor (except for

fXTAL)

CL = 30 pF; note 5

−

slew rate

slew up or down; CL = 30 pF

0.2

−−

V/ns

Control inputs (pins CLKDIV1, CLKDIV2, CMDVCC, RSTIN and 5V/3V); note 6

VIL

LOW-level input voltage

−0.3

−

+0.3VDD

VIH

HIGH-level input voltage

0.7VDD

−

VDD + 0.3 V

ILIL

LOW-level input leakage

current

0<VIL <VDD

−−

µA

ILIH

HIGH-level input leakage

current

0<VIH <VDD

−−

µA

Card presence inputs (pins PRES and PRES); note 7

VIL

LOW-level input voltage

−0.3

−

+0.3VDD

VIH

HIGH-level input voltage

0.7VDD

−

VDD + 0.3 V

ILIL

LOW-level input leakage

current

0<VIL <VDD

−−

µA

ILIH

HIGH-level input leakage

current

0<VIH <VDD

−−

µA

Interrupt output (pin OFF; NMOS drain with integrated 20 k

Ω pull-up resistor to VDD)

VOL

LOW-level output voltage

IOL = 2 mA

−

0.3

VOH

HIGH-level output voltage

IOH = −15 µA

0.75VDD

−−

Rpu

integrated pull-up resistor

20 k

Ω pull-up resistor to VDD

Ω

Protection and limitation

ICC(sd)

shutdown and limitation

current pin VCC

−

130

150

II/O(lim)

limitation current pins I/O,

AUX1 and AUX2

−15

−

+15

ICLK(lim)

limitation current pin CLK

−70

−

+70

IRST(lim)

limitation current pin RST

−20

−

+20

Tsd

shut-down temperature

−

150

−°C

Timing

tact

activation time

see Fig.7

−

220

µs

tde

deactivation time

see Fig.8

100

µs

start of the window for

sending CLK to the card

see Fig.7

−

130

µs

end of the window for

sending CLK to the card

see Fig.7

140

−

220

µs

tdebounce

debounce time pins PRES

and PRES

see Fig.10

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP

MAX.

UNIT

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