TMS320C6472ECTZ datasheet(154/269 Pages) TI1

154 / 269 page

TMS320C6472

SPRS612G

– JUNE 2009 – REVISED JULY 2011

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7.8.3.3

PLL1 PLL Control Register (PLLCTL)

The PLL control register (PLLCTL) is shown in Figure 7-16 and described in Table 7-22.

Reserved

R-00 0001h

PLL

Reserved

Rsvd

Reserved

PLLRST

Rsvd

PLLEN

PWRDN

R-00 0001h

R/W-0

R-1

R/W-10

R/W-1

R-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Figure 7-16. PLL Control Register (PLLCTL)

Table 7-22. PLL Control Register (PLLCTL) Field Descriptions(1)

Bit

Field

Value

Description

31:8

Reserved

Reserved. The reserved bit location is always read as 00 0001h. A value written to this field has no

effect.

Reserved

Reserved. Writes to this register must keep this bit as 0.

Reserved

Reserved. The reserved bit location is always read as 1. A value written to this field has no effect.

5:4

Reserved

Reserved. Writes to this register must always program these bits as 00.

PLLRST

PLL reset bit

PLL reset is released

PLL reset is asserted

Reserved

Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.

PLLPWRDN

PLL power-down mode select bit

PLL is operational

PLL is placed in power-down state, i.e., all analog circuitry in the PLL is turned-off

PLLEN

PLL enable bit

Bypass mode. PLL is bypassed. All the system clocks (SYSCLKn) are divided down directly from

input reference clock (CLKIN1).

PLL mode. PLL is not bypassed. PLL output path is enabled. All the system clocks (SYSCLKn) are

divided down from PLL output.

(1)

The value of this register is changed by the ROM bootloader.

154

C64x+ Peripheral Information and Electrical Specifications

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