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1 / 269 page  TMS320C6472 www.ti.com SPRS612G – JUNE 2009 – REVISED JULY 2011 TMS320C6472 Fixed-Point Digital Signal Processor 1 Features 1 Congestion Control • Six On-Chip TMS320C64x+ Megamodules • IEEE 1149.6 Compliant I/Os • Endianess: Little Endian, Big Endian – UTOPIA • C64x+ Megamodule Main Features: • UTOPIA Level 2 Slave ATM Controller – High-Performance, Fixed-Point TMS320C64x+ DSP • 8/16-Bit Transmit and Receive Operations up to 50 MHz per Direction – 500/625/700 MHz • User-Defined Cell Format up to 64 Bytes – Eight 32-Bit Instructions/Cycle – Two 10/100/1000 Mb/s Ethernet MACs – 4000 MIPS/MMACS (16-Bits) at 500 MHz (EMACs) – Dedicated SPLOOP Instruction • Both EMACs are IEEE 802.3 Compliant – Compact Instructions (16-Bit) • EMAC0 Supports: – Instruction Set Enhancements – MII, RMII, SS-SMII, GMII, and RGMII – Exception Handling – 8 Independent Transmit (TX) – L1/L2 Memory Architecture: Channels • 256K-Bit (32K-Byte) L1P Program – 8 Independent Receive (RX) RAM/Cache [Direct Mapped, Flexible Channels Allocation] • EMAC1 Supports: • 256K-Bit (32K-Byte) L1D RAM/Cache – RMII, SS-SMII and RGMII [2-Way Set-Associative, Flexible Allocation] – 8 Independent Transmit (TX) Channels • 4.75M-Bit (608K-Byte) L2 Unified Mapped RAM/Cache [4-Way Set-Associative, – 8 Independent Receive (RX) Flexible Allocation] Channels • L1P Memory Controller • Both EMACs (EMAC0 and EMAC1) Share MDIO Interface • L1D Memory Controller – 16-Bit Host-Port Interface (HPI) • L2 Memory Controller – One Inter-Integrated Circuit (I2C) Bus – Time Stamp Counter – Six Shared 64-Bit General-Purpose Timers – One 64-Bit General-Purpose/Watchdog Timer • System PLL and PLL Controller • Shared Peripherals and Interfaces • Secondary PLL and PLL Controller, Dedicated – EDMA Controller to EMAC (64 Independent Channels) • Third PLL and PLL Controller Dedicated to – Shared Memory Architecture DDR2 Memory Controller • Shared L2 Memory Controller • 16 General-Purpose I/O (GPIO) Pins • 768K-Byte of RAM • IEEE-1149.1 (JTAG™) • Boot ROM Boundary-Scan-Compatible – Three Telecom Serial Interface Ports (TSIPs) • 737-Pin Ball Grid Array (BGA) Package • Each TSIP is 8 Links of 8 Mbps per (CTZ or ZTZ Suffix), 0.8-mm Ball Pitch Direction • 0.09-μm/7-Level Cu Metal Process (CMOS) – 32-Bit DDR2 Memory Controller (DDR2-533 • 3.3-, 1.8-, 1.5-, 1.2-V I/O Supplies SDRAM) • 1.0-/1.1-, 1.2-V Core Supplies • 256 M-Byte x 2 Addressable Memory • Commercial Temperature [0°C to 85°C] Space • Extended Temperature [-40°C to 100°C] – Two 1x Serial RapidIO® Links, v1.2 Compliant • 1.25-, 2.5-, 3.125-Gbps Link Rates • Message Passing, DirectIO Support, Error Management Extensions, and 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCT PREVIEW information concerns products in the formative Copyright © 2009–2011, Texas Instruments Incorporated or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. |
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