TMS320C6472ECTZ datasheet(137/269 Pages) TI1

137 / 269 page

TMS320C6472

www.ti.com

SPRS612G

– JUNE 2009 – REVISED JULY 2011

7.6

Interrupts

7.6.1

Interrupt Sources and Interrupt Controller

The CPU interrupts on the C6472 device are configured through the C64x+ megamodule interrupt

controller. The interrupt controller allows for up to 128 system events to be programmed to any of the

twelve CPU interrupt inputs, the CPU exception input, or the advanced emulation logic. Table 8-4 shows

the mapping of system events to the interrupt controller inputs. Event numbers 0-31 correspond to the

default interrupt mapping of the device. The remaining events must be mapped using software.

For more information on the Interrupt Controller, see the TMS320C64x+ DSP Megamodule Reference

Guide (literature number SPRU871).

Table 7-10. C6472 DSP Interrupts

EVENT NUMBER

INTERRUPT EVENT

INTERRUPT SOURCE

0(1)

EVT0

Event Combiner 0 Output

1(1)

EVT1

Event Combiner 1 Output

2(1)

EVT2

Event Combiner 2 Output

3(1)

EVT3

Event Combiner 3 Output

4(2)

RIOINT_LOCAL

RapidIO Individual Interrupt

MACRXINT0

Ethernet MAC0 Receive Interrupt

MACTXINT0

Ethernet MAC0 Transmit Interrupt

MACRXINT1

Ethernet MAC1 Receive Interrupt

MACTXINT1

Ethernet MAC1 Transmit Interrupt

ECM Interrupt for:

•

Host scan access

9(1)

EMU_D

•

DTDMA transfer complete

•

AET interrupt

Reserved

11(1)

EMU_RTDXRX

RTDX Receive Complete

12(1)

EMU_RTDXTX

RTDX Transmit Complete

13(1)

IDMA0

IDMA Channel 0 Interrupt

14(1)

IDMA1

IDMA Channel 1 Interrupt

15(3)

EDMA3CCINT_LOCAL

EDMA3CC Individual Completion Interrupt

TINTL

Local Timer Interrupt Low

TINTH

Local Timer Interrupt High

TINT6L

Timer 6 Interrupt Low

TINT6H

Timer 6 Interrupt High

TINT7L

Timer 7 Interrupt Low

TINT7H

Timer 7 Interrupt High

TINT8L

Timer 8 Interrupt Low

TINT8H

Timer 8 Interrupt High

TINT9L

Timer 9 Interrupt Low

TINT9H

Timer 9 Interrupt High

TINT10L

Timer 10 Interrupt Low

TINT10H

Timer 10 Interrupt High

TINT11L

Timer 11 Interrupt Low

TINT11H

Timer 11 Interrupt High

UTOPIA-PDMA Receive Interrupt

PXINT

UTOPIA-PDMA Transmit Interrupt

(1)

This system event is generated from within the C64x+ megamodule.

(2)

RIO_INT0 to RIO_INT5 are routed to Core0 to Core5, respectively.

(3)

EDMA3CC_INT0 (MASK 0) to EDMA3CC_INT5 (MASK 5) are routed to Core0 to Core5, respectively.

C64x+ Peripheral Information and Electrical Specifications

137

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