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TMS570LS0332PZ 데이터시트(PDF) 33 Page - Texas Instruments

부품명 TMS570LS0332PZ
상세설명  16- and 32-Bit RISC Flash Microcontroller
PDF  110 Pages
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제조업체  TI1 [Texas Instruments]
홈페이지  http://www.ti.com
Logo TI1 - Texas Instruments

TMS570LS0332PZ 데이터시트(HTML) 33 Page - Texas Instruments

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TMS570LS0432, TMS570LS0332
www.ti.com
SPNS186B – OCTOBER 2012 – REVISED JUNE 2015
6.4.6.1
Application Sequence for CPU Self-Test
1. Configure clock domain frequencies.
2. Select the number of test intervals to be run.
3. Configure the timeout period for the self-test run.
4. Save the CPU state if required
5. Enable self-test.
6. Wait for CPU reset.
7. In the reset handler, read CPU self-test status to identify any failures.
8. Retrieve CPU state if required.
For more information, see the TMS570LS04x/03x 16/32-Bit RISC Flash Microcontroller Technical
Reference Manual (SPNU517).
6.4.6.2
CPU Self-Test Clock Configuration
The maximum clock rate for the self-test is 45 MHz. The STCCLK is divided down from the CPU clock,
when necessary. This divider is configured by the STCCLKDIV register at address 0xFFFFE108.
6.4.6.3
CPU Self-Test Coverage
Table 6-7 shows CPU test coverage achieved for each self-test interval. It also lists the cumulative test
cycles. The test time can be calculated by multiplying the number of test cycles with the STC clock period.
Table 6-7. CPU Self-Test Coverage
INTERVALS
TEST COVERAGE, %
TEST CYCLES
0
0
0
1
60.06
1365
2
68.71
2730
3
73.35
4095
4
76.57
5460
5
78.7
6825
6
80.4
8190
7
81.76
9555
8
82.94
10920
9
83.84
12285
10
84.58
13650
11
85.31
15015
12
85.9
16380
13
86.59
17745
14
87.17
19110
15
87.67
20475
16
88.11
21840
17
88.53
23205
18
88.93
24570
19
89.26
25935
20
89.56
27300
21
89.86
28665
22
90.1
30030
23
90.36
31395
24
90.62
32760
Copyright © 2012–2015, Texas Instruments Incorporated
System Information and Electrical Specifications
33
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Product Folder Links: TMS570LS0432 TMS570LS0332



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