TMS570LS1114 datasheet(76/169 Pages) TI1

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TMS570LS1114

SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015

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6.10.3 ECC Protection for Flash Accesses

All accesses to the program flash memory are protected by Single Error Correction Double Error Detection

(SECDED) logic embedded inside the CPU. The flash module provides 8 bits of ECC code for 64 bits of

instructions or data fetched from the flash memory. The CPU calculates the expected ECC code based on

the 64 bits received and compares it with the ECC code returned by the flash module. A single-bit error is

corrected and flagged by the CPU, while a multibit error is only flagged. The CPU signals an ECC error

through its Event bus. This signaling mechanism is not enabled by default and must be enabled by setting

the "X" bit of the Performance Monitor Control Register, c9.

MRC p15,#0,r1,c9,c12,#0

;Enabling Event monitor states

ORR r1, r1, #0x00000010

MCR p15,#0,r1,c9,c12,#0

;Set 4th bit (‘X’) of PMNC register

MRC p15,#0,r1,c9,c12,#0

The application must also explicitly enable the CPU's ECC checking for accesses on the CPU's ATCM

and BTCM interfaces. These are connected to the program flash and data RAM respectively. ECC

checking for these interfaces can be done by setting the B1TCMPCEN, B0TCMPCEN and ATCMPCEN

bits of the System Control coprocessor's Auxiliary Control Register, c1.

MRC p15, #0, r1, c1, c0, #1

ORR r1, r1, #0x0e000000

;Enable ECC checking for ATCM and BTCMs

DMB

MCR p15, #0, r1, c1, c0, #1

6.10.4 Flash Access Speeds

For information on flash memory access speeds and the relevant wait states required, refer to Section 5.6.

System Information and Electrical Specifications

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