MCP14A0153_15 datasheet(13/30 Pages) MICROCHIP

13 / 30 page

 2015 Microchip Technology Inc.

DS20005470A-page 13

MCP14A0153/4/5

FIGURE 4-3:

Enable Timing Waveform.

4.4

Decoupling Capacitors

Careful PCB layout and decoupling capacitors are

required when using power MOSFET drivers. Large

current is required to charge and discharge capacitive

loads quickly. For example, approximately 720 mA are

needed to charge a 1000 pF load with 18V in 25 ns.

To operate the MOSFET driver over a wide frequency

range with low supply impedance, it is recommended to

place 1.0 µF and 0.1 µF low ESR ceramic capacitors in

parallel between the driver VDD and GND. These

capacitors should be placed close to the driver to

minimize circuit board parasitics and provide a local

source for the required current.

4.5

PCB Layout Considerations

Proper Printed Circuit Board (PCB) layout is important

in high-current, fast switching circuits to provide proper

device operation and robustness of design. Improper

component placement may cause errant switching,

excessive voltage ringing or circuit latch-up. The PCB

trace loop length and inductance should be minimized

by the use of ground planes or traces under the

MOSFET gate drive signal. Separate analog and

power grounds and local driver decoupling should also

be used.

Placing a ground plane beneath the MCP14A0153/4/5

devices will help as a radiated noise shield, as well as

providing some heat sinking for power dissipated within

the device.

4.6

Power Dissipation

The total internal power dissipation in a MOSFET driver

is the summation of three separate power dissipation

elements, as shown in Equation 4-1.

EQUATION 4-1:

4.6.1

CAPACITIVE LOAD DISSIPATION

The power dissipation caused by a capacitive load is a

direct function of the frequency, total capacitive load

and supply voltage. The power lost in the MOSFET

driver for a complete charging and discharging cycle of

a MOSFET is shown in Equation 4-2.

EQUATION 4-2:

4.6.2

QUIESCENT POWER DISSIPATION

The power dissipation associated with the quiescent

current draw depends on the state of the Input and

Enable

pins.

See

Section 1.0

“Electrical

Characteristics”

for typical quiescent current draw

values in different operating states. The quiescent

power dissipation is shown in Equation 4-3.

EQUATION 4-3:

TABLE 4-1:

ENABLE PIN LOGIC

OUT

tD3

10%

90%

Enable

Output

18V

VEH (Typ.)

VEL (Typ.)

tD4

Where:

PT = Total power dissipation

PL = Load power dissipation

PQ = Quiescent power dissipation

PCC = Operating power dissipation



Where:

Switching frequency

CT = Total load capacitance

VDD = MOSFET driver supply voltage

–





 V



Where:

IQH = Quiescent current in the High state

Duty cycle

IQL = Quiescent current in the Low state

VDD =

MOSFET driver supply voltage

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