| 전자부품 데이터시트 검색엔진 |
|
K4S561633C-RBL 데이터시트(PDF) 2 Page - Samsung semiconductor |
|
|
|||||||||||||||||||||||||||||
K4S561633C-RBL 데이터시트(HTML) 2 Page - Samsung semiconductor |
|
2 / 8 page ![]() K4S561633C-R(B)L/N/P Rev. 1.4 Dec. 2002 CMOS SDRAM • 3.0V & 3.3V power supply. • LVCMOS compatible with multiplexed address. • Four banks operation. • MRS cycle with address key programs. -. CAS latency (1 & 2 & 3). -. Burst length (1, 2, 4, 8 & Full page). -. Burst type (Sequential & Interleave). • All inputs are sampled at the positive going edge of the system clock. • Burst read single-bit write operation. • DQM for masking • Auto refresh. • 64ms refresh period (8K cycle). • Commercial Temperature Operation (-25 °C ~ 70°C). Extended Temperature Operation ( -25 °C ~ 85°C). Inderstrial Temperature Operation ( -40 °C ~ 85°C). • 54balls CSP (-RXXX - Pb, -BXXX - Pb Free) FEATURES GENERAL DESCRIPTION 4M x 16Bit x 4 Banks Synchronous DRAM in 54CSP FUNCTIONAL BLOCK DIAGRAM The K4S561633C is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 4 x 4,196,304 words by 16 bits, fabri- cated with SAMSUNG's high performance CMOS technology. Syn- chronous design allows precise cycle control with the use of system clock and I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. Bank Select Data Input Register 4M x 16 4M x 16 Column Decoder Latency & Burst Length Programming Register LCKE LRAS LCBR LWE LDQM CLK CKE CS RAS CAS WE L(U)DQM LWE LDQM DQi CLK ADD LCAS LWCBR 4M x 16 4M x 16 Timing Register * Samsung Electronics reserves the right to change products or specification without notice. ORDERING INFORMATION -R(B)L ; Low Power, Operating Temp : -25 °C ~ 70°C. -R(B)N ; Low Power, Operating Temp : -25 °C ~ 85°C. -R(B)P : Low Power, Operating Temp : -40 °C ~ 85°C. Note : 1. In case of 40MHz Frequency, CL1 can be supported. Part No. Max Freq. Interface Package K4S561633C-R(B)L/N/P75 133MHz(CL=3) 105MHz(CL=2) LVCMOS 54 CSP Pb (Pb Free) K4S561633C-R(B)L/N/P1H 105MHz(CL=2) K4S561633C-R(B)L/N/P1L 105MHz(CL=3)*1 |
|
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |