VT8231 datasheet(16/132 Pages) ETC

16 / 132 page

VT8231

Preliminary Revision 0.8 October 29, 1999

-10-

Pinouts

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Pin Descriptions

Table 1. Pin Descriptions

PCI Bus Interface

Signal Name

Pin #

I/O

Signal Description

AD[31:0]

(see pin

list)

Address/Data Bus. The standard PCI address and data lines. The address is driven with

FRAME# assertion and data is driven or received in following cycles.

C/BE[3:0]#

C5, D6,

A8, F10

Command/Byte Enable.

The command is driven with FRAME# assertion.

Byte

enables corresponding to supplied or requested data are driven on following clocks.

FRAME#

Frame. Assertion indicates the address phase of a PCI transfer. Negation indicates that

one more data transfer is desired by the cycle initiator.

IRDY#

Initiator Ready. Asserted when the initiator is ready for data transfer.

TRDY#

Target Ready. Asserted when the target is ready for data transfer.

STOP#

Stop. Asserted by the target to request the master to stop the current transaction.

DEVSEL#

Device Select. The VT8231 asserts this signal to claim PCI transactions through positive

or subtractive decoding.

As an input, DEVSEL# indicates the response to a VT8231-

initiated transaction and is also sampled when decoding whether to subtractively decode

the cycle.

PAR

Parity. A single parity bit is provided over AD[31:0] and C/BE[3:0]#.

SERR#

System Error. SERR# can be pulsed active by any PCI device that detects a system

error condition.

Upon sampling SERR# active, the VT8231 can be programmed to

generate an NMI to the CPU.

PINTA-D#

B2, B1,

C3, C2

PCI Interrupt Request. These pins are typically connected to the PCI bus INTA#-

INTD# pins as follows:

PINTA#

PINTB#

PINTC#

PINTD#

PCI Slot 1

INTA#

INTB#

INTC#

INTD#

PCI Slot 2

INTB#

INTC#

INTD#

INTA#

PCI Slot 3

INTC#

INTD#

INTA#

INTB#

PCI Slot 4

INTD#

INTA#

INTB#

INTC#

PCI Slot 5

INTA#

INTB#

INTC#

INTD#

PREQH#

PCI Request. This signal goes to the North Bridge to request the PCI bus.

PGNTH#

PCI Grant.

This signal is driven by the North Bridge to grant PCI access to the

VT8231.

PREQL#

PCI Request. This signal goes to the North Bridge to request the PCI bus.

PGNTL#

PCI Grant.

This signal is driven by the North Bridge to grant PCI access to the

VT8231.

PCICLK

M17

PCI Clock. PCLK provides timing for all transactions on the PCI Bus.

PCKRUN#

PCI Bus Clock Run. This signal indicates whether the PCI clock is or will be stopped

(high) or running (low). The VT8231 drives this signal low when the PCI clock is

running (default on reset) and releases it when it stops the PCI clock. External devices

may assert this signal low to request that the PCI clock be restarted or prevent it from

stopping. Connect this pin to ground using a 100

Ω resistor if the function is not used.

Refer to the “PCI Mobile Design Guide” and the VIA “Apollo MVP4 Design Guide” for

more details.

PCIRST#

PCI Reset.

PCISTP# / GPO6

PCI Stop.

CPUSTP# / GPO5

CPU Stop.

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