Undervoltage

Lockout

Thermal

Shutdown

Softstart

Control

Logic

PMOS

Valley

Current

Sense

V

REF

VOUT

GND

SW

VIN

NMOS

Modulator

BP

EN

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TPS61253, TPS61254, TPS61256, TPS61258, TPS61259, TPS612592

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SLVSAG8G – SEPTEMBER 2011 – REVISED JUNE 2016

Product Folder Links: TPS61253 TPS61254 TPS61256 TPS61258 TPS61259 TPS612592

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Copyright © 2011–2016, Texas Instruments Incorporated

9 Detailed Description

9.1 Overview

The TPS6125x synchronous step-up converter typically operates at a quasi-constant 3.5-MHz frequency pulse

width modulation (PWM) at moderate to heavy load currents. At light load currents, the TPS6125x converter

operates in power-save mode with pulse frequency modulation (PFM).

During PWM operation, the converter uses a novel quasi-constant on-time valley current mode control scheme to

achieve excellent line/load regulation and allows the use of a small ceramic inductor and capacitors. Based on

At the beginning of the switching cycle, the low-side N-MOS switch is turned-on and the inductor current ramps

up to a peak current that is defined by the on-time and the inductance. In the second phase, once the on-timer

has expired, the rectifier is turned-on and the inductor current decays to a preset valley current threshold. Finally,

the switching cycle repeats by setting the on timer again and activating the low-side N-MOS switch.

In general, a dc/dc step-up converter can only operate in "true" boost mode, i.e. the output “boosted” by a certain

amount above the input voltage. The TPS6125x device operates differently as it can smoothly transition in and

out of zero duty cycle operation. Therefore the output can be kept as close as possible to its regulation limits

even though the converter is subject to an input voltage that tends to be excessive. In this operation mode, the

output current capability of the regulator is limited to ca. 150mA. Refer to Figure 11 for further details.

The current mode architecture with adaptive slope compensation provides excellent transient load response,

requiring minimal output filtering. Internal soft-start and loop compensation simplifies the design process while

minimizing the number of external components.

9.2 Functional Block Diagram