PLL1700

3

SBOS096A

www.ti.com

ELECTRICAL CHARACTERISTICS

PLL1700E

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

DIGITAL INPUT/OUTPUT

Input Logic Level:

TTL-Compatible

2.0

VDC

0.8

VDC

1.2

VDC

0.4

VDC

Input Logic Current:

200

µA

–1

µA

4mA

–800

µA

Output Logic Level:

CMOS

VDC

0.4

VDC

32

44.1

48

kHz

64

88.2

96

kHz

MASTER CLOCK (MCKO, MCKO)

Master Clock Frequency

26.73

27

27.27

MHz

300

ps

Clock Duty Cycle

MCKO

40

50

60

%

For Crystal Oscillation

MCKO

40

50

60

%

Clock Duty Cycle

MCKO

40

%

For External Clock

MCKO

60

%

PHASE LOCK LOOP (PLL)

Generated System Clock Frequency

SCKO1

Fixed

33.8688

MHz

SCKO2

8.192

24.576

MHz

SCKO3

12.288

36.864

MHz

SCKO4

24.576

36.864

MHz

5ns

5ns

Generated Clock Duty Cycle

SCKO1, SCKO3, SCKO4

40

50

60

%

SCKO2 (standard)

40

50

60

%

25

33

40

%

SCKO1, SCKO2 (standard), SCKO4

300

ps

SCKO3

150

ps

SCKO2 (double)

450

ps

Settling Time

To Programmed Frequency

20

ms

Power-Up Time

To Programmed Frequency

15

30

ms

POWER SUPPLY REQUIREMENTS

Voltage Range

+4.5

+5

+5.5

VDC

+2.7

+3.3

+3.6

VDC

11

16

mA

6

9

mA

Power Dissipation

75

110

mW

TEMPERATURE RANGE

Operation

–25

+85

°C

Storage

–55

+125

°C

NOTES: (1) ML, MC, MD, MODE, RST (Schmitt-trigger input with internal pull-down resistor).

(2) XT1, when an external 27MHz clock is used, the buffer ICs, such as 74HC04, are recommended to interface to XT1.

(3) MCKO, MCKO, SCKO4, SCKO3, SCKO2, and SCKO1.

(4) Jitter performance is specified as standard deviation of jitter under 27MHz crystal oscillation.

(5) When SCKO2 is set to double rate clock output, its duty cycle is 33%.