49%

FPO

PLL1700

MULTI-CLOCK GENERATOR

FEATURES

q 27MHz MASTER CLOCK INPUT

q GENERATED AUDIO SYSTEM CLOCK:

SCKO1: 33.8688MHz (Fixed)

q ZERO PPM ERROR OUTPUT CLOCKS

q LOW CLOCK JITTER: 150ps at SCKO3

q MULTIPLE SAMPLING FREQUENCIES:

88.2kHz, 96kHz

q +3.3V CMOS LOGIC INTERFACE

q DUAL POWER SUPPLIES: +5V and +3.3V

q SMALL PACKAGE: 20-Lead SSOP

OSC

PLL2

PLL1

Counter Q

Counter P

SCKO2

SCKO3

SCKO4

MCKO

MCKO

XT1

XT2

Reset

Mode

Control

I/F

Power Supply

RST

MODE

ML

MC

MD

V

DDP

V

DDB

V

DD

GNDP

GNDB

GND

SCKO1

®

PLL1

700

SBOS096A – JANUARY 1998 – REVISED MAY 2007

www.ti.com

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Copyright © 1998-2007, Texas Instruments Incorporated

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

DESCRIPTION

The PLL1700 is a low cost, multi-clock generator Phase

Lock Loop (PLL).

The PLL1700 can generate four systems clocks from a

27MHz reference input frequency.

The device gives customers both cost and space savings

by eliminating external components and enables custom-

ers to achieve the very low jitter performance needed for

high-performance audio digital-to-analog converters

(DACs) and/or analog-to-digital converters (ADCs).

The PLL1700 is ideal for MPEG-2 applications that use a

27MHz master clock such as DVD players, DVD add-on

cards for multimedia PCs, digital HDTV systems, and set-

top boxes.