®

19

PCM3500

SYMBOL

DESCRIPTION

MIN

TYP

MAX

UNITS

BCK Period

600

4000

ns

BCK Pulse Width HIGH

300

2000

ns

BCK Pulse Width LOW

300

2000

ns

Delay Time BCK Falling Edge to FS

–40

40

ns

FS Pulse Width HIGH

ns

FS Period

DIN Set Up Time to BCK Rising Edge

60

ns

DIN Hold Time to BCK Rising Edge

60

ns

Delay Time BCK Falling Edge to DOUT

0

80

ns

Delay Time BCK Falling Edge to DOUT Active

20

ns

Delay Time BCK Falling Edge to DOUT Inactive

19.5

ns

FSO Pulse Width HIGH

ns

Delay Time BCK Falling Edge to FSO

0

80

ns

Rising Time of All Signals

30

ns

Falling Time of All Signals

30

ns

FIGURE 14. Serial Interface Timing for Time Slot Mode Operation (Master Mode).

FIGURE 15. High-Pass Filter Response.

HIGH-PASS FILTER FREQUENCY RESPONSE

STOPBAND CHARACTERISTICS

Normalized Frequency (• f

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0.1

0.2

0.3

0.4

0.5

0

HIGH-PASS FILTER FREQUENCY RESPONSE

PASSBAND CHARACTERISTICS

Normalized Frequency (• f

0.0

–0.1

–0.2

–0.3

–0.4

–0.5

–0.6

–0.7

–0.8

–0.9

–10

12

3

4

0

t

FSW

High Impedance

High Impedance

t

BCKP

t

CKFS

t

BCKL

t

DISU

t

DIHD

t

BCKH

t

CKDO

t

HZDO

t

DOHZ

t

FSP

NOTES: Timing measurement reference level is (VIH/VIL)/2. Rising and falling time is measured from

10% to 90% of IN/OUT signal swing. Load capacitance of DOUT, FSO, FS, and BCK signal is 50pF.

0.5V

DD

0.5V

DD

0.5V

DD

0.5V

DD

0.5V

DD

t

FSOW

t

BFSO

FS

(output)

BCK

(output)

DIN

(input)

DOUT

(output)

FSO

(output)