4

MPC185 Security Processor Technical Summary

MOTOROLA

5 Architectural Overview

A block diagram of the MPC185 internal architecture is shown in Figure 5-3. The 60x bus interface (60x/IF)

module is designed to transfer 64-bit words between the 60x bus and any register inside the MPC185.

An operation begins with a write of a pointer to a crypto-channel fetch register which points to a data packet

descriptor. The channel requests the descriptor and decodes the operation to be performed. The channel then

requests the controller to assign crypto execution units and fetch the keys, IV’s and data needed to perform

the given operation. The controller satisfies the requests by assigning execution units to the channel and by

making requests to the master interface per the programmable priority scheme. As data is processed, it is

written to the individual execution units output buffer and then back to system memory via the 60x/IF

module.

Figure 5-3. MPC185 Functional Blocks

6 Data Packet Descriptors

As a crypto accelerator, the MPC185 controller has been designed for easy use and integration with existing

systems and software. All cryptographic functions are accessible through data packet descriptors, some of

which have been defined as multifunction to facilitate IPSec applications. A data packet descriptor is

diagrammed in Table 6-1.

Table 6-1. Example Data Packet Descriptor

Field Name

Value/Type

Description

DPD_DES_CTX_CRYPT

Tbd

Representative header for DES using Context to Encrypt

LEN_CTXIN

PTR_CTXIN

Length

Pointer

Number of bytes to be written

Pointer to Context (IV) to be written into DES engine

LEN_KEY

PTR_KEY

Length

Pointer

Number of bytes in key

Pointer to block cipher key

LEN_DATAIN

PTR_DATAIN

Length

Pointer

Number of bytes of data to be ciphered

Pointer to data to perform cipher upon

crypto-

channel

crypto-

channel

crypto-

channel

crypto-

channel

60x

Control

PKEU

DEU

FIFO

FIFO

FIFO

FIFO

KEU

FIFO

RNG

FIFO

FIFO

AFEU

32KB

gpRAM

FIFO

MDEU

Master/Slave

Interface

AESU

FIFO

FIFO

x2

x2

x2

x2

Freescale Semiconductor, Inc.

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