MPC8272CVRB datasheet(21/56 Pages) MOTOROLA

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MPC8272 PowerQUICC II™ Family Hardware Speciﬁcations

MOTOROLA

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

AC Electrical Characteristics

NOTE

Generally, all MPC8272 bus and system output signals are driven from the

rising edge of the input clock (CLKin). Memory controller signals,

however, trigger on four points within a CLKin cycle. Each cycle is

divided by four internal ticks: T1, T2, T3, and T4. T1 always occurs at the

rising edge, and T3 at the falling edge, of CLKin. However, the spacing of

T2 and T4 depends on the PLL clock ratio selected, as shown in Table 13.

Figure 11 is a representation of the information in Table 13.

Figure 11. Internal Tick Spacing for Memory Controller Signals

NOTE

The UPM machine outputs change on the internal tick determined by the

memory controller programming; the AC speciﬁcations are relative to the

internal tick. Note that SDRAM and GPCM machine outputs change on

CLKin’s rising edge.

Table 13. Tick Spacing for Memory Controller Signals

PLL Clock Ratio

Tick Spacing (T1 Occurs at the Rising Edge of CLKin)

1:2, 1:3, 1:4, 1:5, 1:6

1/4 CLKin

1/2 CLKin

3/4 CLKin

1:2.5

3/10 CLKin

1/2 CLKin

8/10 CLKin

1:3.5

4/14 CLKin

1/2 CLKin

11/14 CLKin

CLKin

for 1:2.5

for 1:3.5

CLKin

for 1:2, 1:3, 1:4, 1:5, 1:6

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

MPC8272CVRB 데이터시트(PDF) 21 Page - Motorola, Inc