P89C668 datasheet(18/89 Pages) PHILIPS

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Philips Semiconductors

Product data

P89C660/P89C662/P89C664/

P89C668

80C51 8-bit Flash microcontroller family

16KB/32KB/64KB ISP/IAP Flash with 512B/1KB/2KB/8KB RAM

2002 Oct 28

If the STA and STO bits are both set, the a STOP condition is

transmitted to the I2C bus if SIO1 is in a Master mode (in a Slave

mode, SIO1 generates an internal STOP condition which is not

transmitted). SIO1 then transmits a START condition.

STO = “0”: When the STO bit is reset, no STOP condition will be

generated.

The Serial Interrupt Flag, SI: SI = “1”: When the SI flag is set, then,

if the EA and ES1 (interrupt enable register) bits are also set, a

serial interrupt is requested. SI is set by hardware when one of 25 of

the 26 possible SIO1 states is entered. The only state that does not

cause SI to be set is state F8H, which indicates that no relevant

state information is available.

While SI is set, the low period of the serial clock on the SCL line is

stretched, and the serial transfer is suspended. A high level on the

SCL line is unaffected by the serial interrupt flag. SI must be reset

by software.

SI = “0”: When the SI flag is reset, no serial interrupt is requested,

and there is no stretching of the serial clock on the SCL line.

The Assert Acknowledge Flag, AA: AA = “1”: If the AA flag is set,

an acknowledge (low level to SDA) will be returned during the

acknowledge clock pulse on the SCL line when:

– The “own slave address” has been received

– The general call address has been received while the general call

bit (GC) in S1ADR is set

– A data byte has been received while SIO1 is in the Master

Receiver mode

– A data byte has been received while SIO1 is in the addressed

Slave Receiver mode

AA = “0”: if the AA flag is reset, a not acknowledge (high level to

SDA) will be returned during the acknowledge clock pulse on SCL

when:

– A data has been received while SIO1 is in the Master Receiver

mode

– A data byte has been received while SIO1 is in the addressed

Slave Receiver mode

When SIO1 is in the addressed Slave Transmitter mode, state C8H

will be entered after the last serial is transmitted (see Figure 11).

When SI is cleared, SIO1 leaves state C8H, enters the not

addressed Slave Receiver mode, and the SDA line remains at a

high level. In state C8H, the AA flag can be set again for future

address recognition.

When SIO1 is in the not addressed Slave mode, its own slave

address and the general call address are ignored. Consequently, no

acknowledge is returned, and a serial interrupt is not requested.

Thus, SIO1 can be temporarily released from the I2C bus while the

bus status is monitored. While SIO1 is released from the bus,

START and STOP conditions are detected, and serial data is shifted

in. Address recognition can be resumed at any time by setting the

AA flag. If the AA flag is set when the part’s own Slave address or

the general call address has been partly received, the address will

be recognized at the end of the byte transmission.

The Clock Rate Bits CR0, CR1, and CR2: These three bits

determine the serial clock frequency when SIO1 is in a Master

mode. The various serial rates are shown in Table 3.

A 12.5 kHz bit rate may be used by devices that interface to the I2C

bus via standard I/O port lines which are software driven and slow.

100 kHz is usually the maximum bit rate and can be derived from a

16 MHz, 12 MHz, or a 6 MHz oscillator. A variable bit rate (0.5 kHz

to 62.5 kHz) may also be used if Timer 1 is not required for any

other purpose while SIO1 is in a Master mode.

The frequencies shown in Table 3 are unimportant when SIO1 is in a

Slave mode. In the Slave modes, SIO1 will automatically

synchronize with any clock frequency up to 100 kHz.

The Status Register, S1STA

S1STA is an 8-bit read-only special function register. The three least

significant bits are always zero. The five most significant bits contain

the status code. There are 26 possible status codes. When S1STA

contains F8H, no relevant state information is available and no serial

interrupt is requested. All other S1STA values correspond to defined

SIO1 states. When each of these states is entered, a serial interrupt

is requested (SI = “1”). A valid status code is present in S1STA one

machine cycle after SI is set by hardware and is still present one

machine cycle after SI has been reset by software.

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