BQ76PL455APFCT datasheet(46/125 Pages) TI1

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bq76PL455A

SLUSCL0A – SEPTEMBER 2016 – REVISED OCTOBER 2016

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Device Functional Modes (continued)

7.4.5 Calculating Wakeup Timing

The following sequence assumes that the microcontroller power circuit provides the VIO supply. The host

microcontroller initiates the sequence and the VIO is up and stable. (The sequence does not change if VIO is tied

to the regulator. However, if some other source is providing WAKEUP, but the microcontroller provides the VIO

supply, the VIO supply needs to clear the POR threshold within VIOSD_DLY of WAKEUP or the part will go back

into shutdown.)

1. The user asserts the WAKEUP pin on the bottom board's base device.

2. At this point, the VP regulator will turn on and ramp the VP/VDIG supplies. The time required to reach the

POR thresholds for VP/VDIG varies and is dependent on the designer's component selection. (Note that

VP/VDIG/VIO must all reach their respective POR thresholds.) Once VP reaches its POR threshold, VREF

will also need to ramp to its operating voltage.

3. The time from reaching the POR thresholds to the start of the wakeup tone being transmitted from the high-

side interface is specified as tWAKEUP_DLY.

4. The time from the start of the wakeup tone being transmitted until communications are allowed to this part is

specified as tWAKEUP_TO_UART.

NOTE

It is acceptable to begin communicating with the part at this point, if it is the only part in

the stack. If there are additional parts in the stack, you can still begin communicating with

the bottom part at this point. However, this may cause communications error flags to get

set in bq76PL455A parts positioned higher in the stack.

5. The time from the wakeup tone transmission from the high side of the device below (end of step 3), until the

regulator turns on the current board, is (tWAKE_TONE_DLY_DC – tWAKEUP_DLY).

6. The regulator turns on and ramps the VP/VDIG/VREF/VIO supplies. As with the bottom device, this time is

board dependent.

7. The time from reaching the POR thresholds to the start of the wakeup tone being transmitted from the high-

side interface to the next device up the stack is specified as tWAKEUP_DLY. Note that for calculation purposes to

group #5 and #7 together as tWAKE_TONE_DLY_DC.

8. The time from the wakeup tone being transmitted from the high-side interface until you are allowed to

communicate with this part is specified as tWAKEUP_TO_DCOMM.

If there are additional parts in the stack, apply steps 5–8 accordingly.

To compute the total time from assertion of WAKEUP to the stack being ready for communications, we will

define:

•

tBOT_RAMP as the time needed for the supply ramp on the bottom board. The above steps must be used to

determine the wakeup time for the bottom board.

•

tSTACK_RAMP as the time needed for the supply ramp on all stacked boards

•

nSTACK_BOARDS as the number of stacked boards (not including the bottom board)

If there is only one device, then the required delay from WAKEUP until it is acceptable to begin communicating

will be:

tBOT_RAMP + tWAKEUP_DLY + tWAKEUP_TO_UART

(8)

Else, if there is more than one board in the stack, the delay from WAKEUP until it is acceptable to begin

communicating will be:

tBOT_RAMP + tWAKEUP_DLY + nSTACK_BOARDS * (tSTACK_RAMP + tWAKE_TONE_DLY_DC) + tWAKEUP_TO_DCOMM

(9)

It is generally acceptable to start communicating with the stack once the bottom UART interface is ready for

communications. However, parts above in the stack may not respond until their required times. It is also possible

to cause communication error flags to be set in the parts above by doing this. As mentioned previously, the

fastest way to get the stack talking (assuming all parts have the EEPROM burned for their stack location and

configuration) may be to continuously send a read request to the top device until it responds and then clear all

communications errors that occur because of this.

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