| 전자부품 데이터시트 검색엔진 |
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DP7112 데이터시트(PDF) 4 Page - Copal Electronics |
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DP7112 데이터시트(HTML) 4 Page - Copal Electronics |
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4 / 10 page ![]() DP7112 4 Table 1. OPERATION MODES INC CS U/D Operation High to Low Low High Wiper toward RH High to Low Low Low Wiper toward RL High Low to High X Store Wiper Position Low Low to High X No Store, Return to Standby X High X Standby Figure 3. Potentiometer Equivalent Circuit CW RL CL CH RWB RWI RH Table 2. ABSOLUTE MAXIMUM RATINGS Parameters Ratings Units Supply Voltage VCC to GND 0.5 to +7 V Inputs CS to GND 0.5 to VCC +0.5 V INC to GND 0.5 to VCC +0.5 V U/D to GND 0.5 to VCC +0.5 V RH to GND 0.5 to VCC +0.5 V RL to GND 0.5 to VCC +0.5 V RWB to GND 0.5 to VCC +0.5 V Operating Ambient Temperature ffix) 40 to +85 C Junction Temperature +150 C Storage Temperature 65 to +150 C Lead Soldering (10 s max) +300 C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Table 3. RELIABILITY CHARACTERISTICS Symbol Parameter Test Method Min Typ Max Units VZAP (Note 1) ESD Susceptibility MIL STD 883, Test Method 3015 2000 V ILTH (Notes 1, 2) Latch Up JEDEC Standard 17 100 mA TDR Data Retention MIL STD 883, Test Method 1008 100 Years NEND Endurance MIL STD 883, Test Method 1003 1,000,000 Stores 1. This parameter is tested initially and after a design or process change that affects the parameter. 2. Latch up protection is provided for stresses up to 100 mA on address and data pins from 1 V to VCC + 1 V |
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