AP0101CS datasheet(4/42 Pages) ONSEMI

4 / 42 page

AP0101CS/D Rev. 7, 1/16 EN

©Semiconductor Components Industries, LLC,2016.

AP0101CS HDR: Image Signal Processor (ISP)

General Description

The ON Semiconductor AP0101CS is a high-performance, ultra-low power in-line,

digital image processor optimized for use with High Dynamic Range (HDR) sensors. The

AP0101CS provides full auto-functions support (AWB and AE) and Adaptive Local Tone

Mapping (ALTM) to enhance HDR images and advanced noise reduction which enables

excellent low-light performance.

Functional Overview

Figure 1 shows the typical configuration of the AP0101CS in a camera system. On the

host side, a two-wire serial interface is used to control the operation of the AP0101CS,

and image data is transferred using the parallel bus between the AP0101CS and the host.

The AP0101CS interface to the sensor also uses a parallel interface.

Figure 1:

AP0101CS Connectivity

System Interfaces

Figure 2 on page 5 shows typical AP0101CS device connections.

All power supply rails must be decoupled from ground using capacitors as close as

possible to the package.

The AP0101CS signals to the sensor and host interfaces can be at different supply voltage

levels to optimize power consumption and maximize flexibility. Table 4 on page 7

provides the signal descriptions for the AP0101CS.

1.2Mp HDR Sensor

12-bit parallel

Host

Up to 20-bit parallel

Two-wire serial I/F (Master)

Two-wire serial IF (Slave)

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