ASX340AT datasheet(21/54 Pages) ONSEMI

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ASX340AT

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TABLE 14. SPI COMMANDS SUPPORTED

Command

Value

Read Array

0x03

Block Erase

0 x D8

Chip Erase

0 x C7

Read Status

0 x 05

Write status

0 x 01

Byte Page Program

0 x 02

Write Enable

0 x 06

Write Disable

0 x 04

Read Manufacturer and Device ID

0 x 9F

(Fast) Read Array

0 x 0B

TABLE 15. GPIO BIT DESCRIPTIONS

GPIO[11] (DOUT_LSB1) GPIO[10] (DOUT_LSB0)

GPIO[9]

(FRAME_VALID

GPI[8] (LINE_VALI

Low (“0”)

Normal

NTSC

Normal

No pedestal

High (“1”)

Vertical Flip

PAL

Horizontal mirror

Pedestal

Host Command Interface

ON Semiconductor sensors and SOCs contain numerous

registers that are accessed through a two-wire interface with

speeds up to 400 kHz.

The ASX340AT in addition to writing or reading straight

to/from registers or firmware variables, has a mechanism to

write higher level commands, the Host Command Interface

(HCI). Once a command has been written through the HCI,

it will be executed by on-chip firmware and the results are

reported back. In general, registers should not be accessed

with the exception of registers that are marked for “User

Access.”

EEPROM or Flash memory is also available to store

commands for later execution. Under DMA control, a

command is written into the SOC and executed.

For a complete description of host commands, refer to the

ASX340AT Host Command Interface Specification.

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