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March 2004

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HIGH SPEED:

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LOW POWER DISSIPATION:

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HIGH NOISE IMMUNITY:

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SYMMETRICAL OUTPUT IMPEDANCE:

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BALANCED PROPAGATION DELAYS:

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WIDE OPERATING VOLTAGE RANGE:

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PIN AND FUNCTION COMPATIBLE WITH

54 SERIES 165

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SPACE GRADE-1: ESA SCC QUALIFIED

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50 krad QUALIFIED, 100 krad AVAILABLE ON

REQUEST

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NO SEL UNDER HIGH LET HEAVY IONS

IRRADIATION

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DEVICE FULLY COMPLIANT WITH

SCC-9306-042

DESCRIPTION

The M54HC165 is an high speed CMOS 8 BIT

PISO SHIFT REGISTER fabricated with silicon

This device contains eight clocked master slave

RS flip-flops connected as a shift register, with

auxiliary

gating

to

provide

over-riding

asynchronous parallel entry. Parallel data enters

when the shift/load input is low. The parallel data

can change while shift/load is low, provided that

the recommended set-up and hold times are

observed. For clocked operation, shift/load must

be high. The two clock input perform identically;

one can be used as a clock inhibit by applying a

high signal; to permit this operation clocking is

accomplished through a 2 input nor gate.

To avoid double clocking, however, the inhibit

signal should only go high while the clock is high.

Otherwise the rising inhibit signal will cause the

same response as rising clock edge.

All inputs are equipped with protection circuits

against static discharge and transient excess

voltage.

M54HC165

RAD-HARD 8 BIT PISO SHIFT REGISTER

PIN CONNECTION

ORDER CODES

PACKAGE

FM

EM

DILC

M54HC165D

M54HC165D1

FPC

M54HC165K

M54HC165K1

DILC-16

FPC-16