TUSB7320 datasheet(45/117 Pages) TI1

45 / 117 page

TUSB7320, TUSB7340

www.ti.com

SLLSE76M – MARCH 2011 – REVISED JULY 2015

Table 74. Link Control 2 Register Description (continued)

BIT

FIELD NAME

ACCESS

DESCRIPTION

Hardware Autonomous Speed Disable. This bit is read only zero

HW_AUTO_SPEED_DIS

because this function is not supported.

ENTER_COMPL(1)

Enter Compliance. This bit is sticky and is only reset by a Global Reset.

3:0

TGT_LINK_SPEED (1)

Target Link Speed. This bit is sticky and is only reset by a Global Reset.

7.5.1.48 Link Status 2 Register

The Link Status 2 Register indicates current state of the PCI Express Link.

PCI register offset: A2h

Default value: 000xh

Table 75. PCI Register A2h

Bit

No.

Reset

State

Table 76. Link Status 2 Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

15:1

RSVD

Reserved. Returns zeros when read.

DEEMPH_LEVEL

Current De-Emphasis Level.

7.5.1.49 Serial Bus Data Register

The Serial Bus Data register is used to read and write data on the serial bus interface. When writing data to the

serial bus, this register must be written before writing to the Serial Bus Address register to initiate the cycle.

When reading data from the serial bus, this register will contain the data read after the REQBUSY (bit 5 Serial

Bus Control Register) bit is cleared. This register is reset by a PCI Express reset (PERST#), a GRST#, or the

internally-generated power-on reset.

PCI register offset: B0h

Default value: 00h

Table 77. PCI Register B0h

Bit No.

Reset State

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