TUSB7320 datasheet(55/117 Pages) TI1

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TUSB7320, TUSB7340

www.ti.com

SLLSE76M – MARCH 2011 – REVISED JULY 2015

7.5.1.64 USB Control Register

This register is a read/write register is used to control USB settings in the TUSB73X0. This register is reset by a

PCI Express reset (PERST#), a GRST#, or the internally-generated power-on reset.

PCI register offset: E0h

Default value: 0000 0000h

Table 103. PCI Register E0h

Bit

No.

Reset

State

Bit

No.

Reset

State

Table 104. USB Control Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

USB Spread Spectrum Disable. When this bit is set to 1, spread

USB_SPREAD_DIS(1)

spectrum generation for the USB 3.0 clock is disabled.

Frequency Select Enable. When this bit is set to 1, the oscillator is

FREQ_SEL_EN(2)

restarted. This bit can only be written to once after power up.

PLL Frequency Select. If the FREQSEL pin is 1, then the value in this

field controls the Frequency Select inputs to the PLL. In addition, the

frequency selector inputs to the Oscillator are set appropriately for the

29:24

PLL_FREQ_SEL(2)

frequency selected. If the FREQSEL pin is 0, then this field has no effect.

Once the FREQ_SEL_EN bit has been set, this field will be locked and

cannot be changed.

Hide MSI-X. When this bit is set, the Next Item Pointer Register (offset

HIDE_MSIX(1)

71h) for the PCI Express Capability is set to 00h, and BAR2 (offset 18h)

and BAR3 (offset 1Ch) are only zeros.

PWRONx Polarity. When this bit is 0 (default), the PWRONx# pins are

active low and their internal pulldown resistors are enabled. When this bit

PWRON_POLARITY(2)

is 1, the PWRONx# pins are active high and their internal pulldown

resistors are disabled.

21:17

RSVD

Reserved. Returns zero when read.

Port Power Control Not Present. When this bit is 0, the TUSB73X0

forces the PPC bit to 1 in the Host Controller Capability Parameters,

indicating that the system supports port power switches. When this bit is

PPC_NOT_PRESENT (1)

set to 1, the TUSB73X0 forces the PPC bit to 0 in the Host Controller

Capability Parameters, indicating that the system does not support port

power switches.

15:12

RSVD(1)

Reserved. Returns zeros when read.

USB Port 4 Disable. When this bit is set to 1, port 4 of the TUSB73X0 is

PORT4_DIS(1)

disabled. For the TUSB7320 Port 4 is not present and this bit has no

effect.

USB Port 3 Disable. When this bit is set to 1, port 3 of the TUSB73X0 is

PORT3_DIS(1)

disabled. For the TUSB7320 Port 3 is not present and this bit has no

effect.

USB Port 2 Disable. When this bit is set to 1, port 2 of the TUSB73X0 is

PORT2_DIS(1)

disabled.

USB Port 1 Disable. When this bit is set to 1, port 1 of the TUSB73X0 is

PORT1_DIS(1)

disabled.

(1)

This bit is reset by a PCI Express reset (PERST), a GRST, or the internally generated power-on reset.

(2)

This bit is a sticky bit and is reset by a global reset (GRST) or the internally-generated poweron reset.

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