LMX2471 datasheet(21/36 Pages) NSC

21 / 36 page

Functional Description (Continued)

1.6.1 Determining the Loop Gain Multiplier, K

The loop bandwidth multiplier, K, is needed in order to de-

termine the theoretical impact of fastlock/CSR on the loop

bandwidth and also which resistor should be switched in

parallel with the loop filter resistor R2. K = K_K · K_Fcomp

where K is the loop gain multiplier K_K is the ratio of the

Fastlock charge pump current to the steady state charge

pump current. Note that this should always be greater than

or equal to one. K_Fcomp is the ratio of the Fastlock com-

parison frequency to the steady state comparison frequency.

If this ratio is less than one, this implies that the CSR is being

used.

1.6.2 Determining the Theoretical Lock Time

Improvement and Fastlock Resistor, R2’

When using fastlock, it is necessary to switch in a resistor

R2’, in parallel with R2 in order to keep the loop filter opti-

mized and maintain the same phase margin. After the PLL

has achieved a frequency that is sufficiently close to the

desired frequency, the resistor R2’ is disengaged and the

charge pump current is and comparison frequency are re-

turned to normal. Of special concern is the glitch that is

caused when the resistor R2’ is disengaged. This glitch can

take up a significant portion of the lock time. The LMX2471

has enhanced switching circuitry to minimize this glitch and

therefore improve the lock time.

20072140

The change in loop bandwidth is dependent upon the loop

gain multiplier, K, as determined in section 4. The theoretical

improvement in lock time is given below, but the actual

improvement will be less than this due to the glitch that is

caused by disengaging Fastlock. The theoretical improve-

ment is given to show an upper bound on what improvement

is possible with Fastlock. In the case that K < 1, this implies

the CSR is being engaged and that the theoretical lock time

will be degraded. However, since this mode reduces or

eliminates cycle slipping, the actual lock time may be better

in cases where the loop bandwidth is small relative to the

comparison frequency. Realize that the theoretical lock time

multiplier does not account for the fastlock/CSR disengage-

ment glitch, which is most severe for larger values of K.

Loop Gain

Multiplier, K

Loop Bandwidth

Multiplier

R2’ Value

Lock Time

Multiplier

1:8*

0.35

open

x 2.828

1:4*

0.50

open

x 2.000

1:2*

0.71

open

x 1.414

4:1

2.00

R2/1.00

x 0.500

8:1

2.83

R2/1.83

x 0.354

16:1

4.00

R2/3.00

x 0.250

32:1

5.66

R2/4.65

x 0.177

* These modes of operation are generally not recommended

1.6.3 Using Fastlock and Cycle Slip Reduction (CSR)

to Avoid Cycle Slipping

In the case that the comparison frequency is very large ( i.e.

100X)ofthe loop bandwidth, cycle slipping may occur when

an instantaneous phase error is presented to the phase

detector. This can be reduced by increasing the loop band-

width during frequency acquisition, decreasing the compari-

son frequency during frequency acquisition, or some combi-

nation of the these. If increasing the loop bandwidth during

frequency acquisition is not sufficient to reduce cycle slip-

ping, the LMX2471 also has a routine to decrease the com-

parison frequency.

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