2.1 R0 REGISTER

Note that this register has only one control bit. The reason for this is that it enables the N counter value to be changed with a

single write statement to the PLL.

REGISTER

23

22

21

20

19

18

17

16

15

14

13

12

11

10

987654

3210

DATA[19:0] ( Except for the RF_N Register, which is [22:0] )

C3

C2

C1

C0

R0

RF_N[10:0]

FN[11:0]

0

2.1.1 RF_FN[11:0] -- Fractional Numerator for RF PLL

Refer to section 2.8.1 for a more detailed description of this control word.

2.1.2 RF_N[10:0] -- RF N Counter Value

The RF N counter contains a 16/17/20/21 prescaler. Because there is only one selection of prescaler, the value that is

programmed is simply the N counter value converted into binary form. However, because this counter does have a prescaler,

there are limitations on the divider values.

RF_N

RF_N[10:0]

RF_C

RF_B

RF_A

≤64

N values less than or equal to 64 are prohibited.

65-66

Possible only with a second order delta-sigma engine

67-70

Possible with a second or third order delta-sigma engine.

71

0000100

0111

72

0000100

1000

...

.......

....

2039

1111111

0111

2040-2043

Possible with a second or third order delta-sigma engine.

2044-2045

Possible only with a second order delta-sigma engine.

N values above 2045 are prohibited.

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