ADPD103 datasheet(49/53 Pages) AD

49 / 53 page

ADPD103

Data Sheet

Rev. B | Page 48 of 52

Address

Data

Bit

Default Access Name

Description

[4:2]

0x0

R/W

SLOTA_FIFO_MODE

Time Slot A FIFO data format.

0: no data to FIFO.

1: 16-bit sample in digital integration mode or 16-bit sum of all

4 channels when not in digital integration mode.

2: 32-bit sample in digital integration mode or 32-bit sum of all

4 channels when not in digital integration mode.

3: 16-bit sample and 16-bit background value in digital integration mode

4: 32-bit sample and 32-bit background value in digital integration

mode or 4 channels of 16-bit sample data for Time Slot B when not in

digital integration mode.

6: 4 channels of 32-bit extended sample data for Time Slot B when not in

digital integration mode.

Others: reserved.

0x0

R/W

Reserved

Write 0x0.

0x0

R/W

SLOTA_EN

Time Slot A enable. 1: enables Time Slot A.

0x38

0x0

R/W

Reserved

Write 0x0.

0x0

R/W

EXT_SYNC_ENA

Enables external sampling trigger.

0x0: samples triggered internally.

0x1: samples triggered externally. Must be set to 1 if EXT_SYNC_SEL is b01 or

b10.

[13:0]

0x0

R/W

Reserved

Write 0x0.

0x4B

[15:9]

0x13

R/W

Reserved

Write 0x13.

0x0

R/W

CLK32K_BYP

Bypass internal 32 kHz clock oscillator.

0x0: normal operation.

0x1: use an external clock on the PDSO pin.

0x0

R/W

CLK32K_EN

Sample clock power-up. Enables the data sample clock.

0x0: clock disabled.

0x1: normal operation.

0x0

R/W

Reserved

Write 0x0.

[5:0]

0x12

R/W

CLK32K_ADJUST

Data sampling (32 kHz) clock frequency adjust. This register is used to

calibrate the sample frequency of the device to achieve high precision

on the data rate as defined in Register 0x12. Adjusts the sample master

32 kHz clock by 0.6 kHz per LSB. For a 100 Hz sample rate as defined in

Note that a larger value produces a lower frequency. See the Clocks and

Timing Calibration section for more information regarding clock

adjustment.

00 0000: maximum frequency.

10 0010: typical center frequency.

11 1111: minimum frequency.

0x4D

[15:8]

0x42

R/W

Reserved

Write 0x42.

[7:0]

0x5E

R/W

CLK32M_ADJUST

Internal timing (32 MHz) clock frequency adjust. This register is used to

calibrate the internal clock of the device to achieve precisely timed LED

pulses. Adjusts the 32 MHz clock by 109 kHz per LSB.

See the Clocks and Timing Calibration section for more information

regarding clock adjustment.

0000 0000: minimum frequency.

0101 1110: default frequency.

1111 1111: maximum frequency.

0x4E1

[15:0]

0x0060

R/W

ADC_TIMING1

0x0040: ADC clock speed = 1 MHz.

0x0060: ADC clock speed = 500 kHz.

ADPD103 데이터시트(PDF) 49 Page - Analog Devices

ADPD103 데이터시트(HTML) 49 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53

데이터시트 다운로드

링크 URL