VDP313XY datasheet(40/76 Pages) MICRONAS

40 / 76 page

VDP 313xY

ADVANCE INFORMATION

Micronas

w/r

Sync Output

bit[5:0]

reserved (set to 0)

bit[7:6]

function of CSY pin

composite sync signal output

25 Hz output (field1/field2 signal)

horizontal sync signal output

1 MHz horizontal drive clock

CSYM

Ports

w/r

IO Port

bit[6:0]

data to/from PORT[6:0]

bit[7]

reserved (set to 0)

bit[14:8]

port direction

switch PORT[bit

−8] to input

switch PORT[bit

−8] to output

bit[15]

reserved (set to 0)

0IOPORT

IODATA

IODIR

Hardware ID

Hardware version number

bit[7:0]

hardware id (A3 = 13, B1 = 21 a.s.o.)

bit[15:8]

product code VDP 31xx Y

(e.g. 32 for VDP 3132 Y)

read

only

HWID

Table 2–5: I2C control and status registers of the video backend

(Registers are set to ’0’ at reset, default values are recommendations)

I2C Sub

address

Number

of bits

Mode

Function

Default

Name

(hex)

VDP313XY 데이터시트(PDF) 40 Page - Micronas

VDP313XY 데이터시트(HTML) 40 Page - Micronas

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76

데이터시트 다운로드

링크 URL