| 전자부품 데이터시트 검색엔진 |
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VDP313XY 데이터시트(PDF) 45 Page - Micronas |
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VDP313XY 데이터시트(HTML) 45 Page - Micronas |
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45 / 76 page ![]() ADVANCE INFORMATION VDP 313xY Micronas 45 Color Processing 30 Saturation control bit[11:0] 0...4094 (2070 corresponds to 100% saturation) 4095 disabled (test mode only) 2070 ACC_SAT 17A bit[10:0] 0...2047 CR-attenuation bit[11] 0/1 disable/enable CR-attenuation 1591 o CR_ATT CR_ATT_ENA 39 bit[10:0] 0...2047 amplitude killer level (0: killer disabled) bit[11] 0/1 disable/enable chroma ADC 25 0 KILVL 3A amplitude killer hysteresis 5 KILHY DC NTSC tint angle, ±512 = ±π/4 0 TINT DVCO F8 crystal oscillator center frequency adjust, −2048...2047 −720 DVCO F9 crystal oscillator center frequency adjustment value for line lock mode,true adjust value is DVCO - ADJUST. For factory crystal alignment, using standard video signal: set DVCO = 0, set lock mode, read crystal offset from ADJUST register and use negative value for initial center frequency adjust- ment via DVCO. read only ADJUST F7 crystal oscillator line-locked mode, lock command/status write: 100 enable lock 0 disable lock read: 0 unlocked >2047 locked 0XLCK B5 crystal oscillator line-locked mode, autolock feature. If autolock is enabled, crystal oscillator locking is started automatically. bit[11:0] threshold; 0: autolock off 400 AUTOLOCK Table 2–6: Control Registers of the Fast Processor for control of the video frontend functions −default values are initializied at reset FP Sub- address Function Default Name (hex) (hex) |
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