VITESSE

SEMICONDUCTOR CORPORATION

Target Specification

VSC8115

STS-12/STS-3 Multi Rate

Clock and Data Recovery Unit

Page 6

© VITESSE SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

9/29/00

G52272-0, Rev. 1.1

Retimed Data and Clock Outputs AC Specification

As indicated in figure 3, it is recommended that the retimed data output be captured with the rising edge of

the clock output. Data valid time is larger for OC-3/STS-3 mode of operation than that of OC-12/STS-12. Data

Figure 3: Retimed Data and Clock Outputs Timing Diagram

Table 3: Retimed Data and Clock Outputs Timing

High Speed Outputs

The high speed output buffers, DATAOUT+/- and CLKOUT+/-, can be terminated as either LVDS or

LVPECL outputs. If used as LVDS outputs, the transmission lines should be routed with 100-ohm differential

impedance, and they need to be terminated at the receive end with a 100-ohm resistor across the differential

pair. If used as LVPECL outputs, the transmission line should be 50-ohm terminated with 50-ohm pull down

resistors near the receiving end.

Parameters

Description

STS-12 Operation

(622.08MHz)

STS-3 Operation

(155.52MHz)

Minimum Available Setup Time

450 pS

2.0 nS

Minimum Available Hold Time

650 pS

3.0 nS

DATAOUT+/-

CLKOUT+