© VITESSE SEMICONDUCTOR CORPORATION

Page 9

9/29/00

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

VITESSE

SEMICONDUCTOR CORPORATION

Target Specification

VSC8115

STS-12/STS-3 Multi Rate

Clock and Data Recovery Unit

G52272-0, Rev. 1.1

Output Current (LVDS or LVPECL Outputs).......................................................................................... +/-50mA

Maximum Input ESD (Human Body Model)

High Speed Outputs (pins 11, 12, 13, & 14) .................................................................................... 500V

All Other Pins ................................................................................................................................. 1500V

Note: Caution: Stresses listed under “Absolute Maximum Ratings” may be applied to devices one at a time without causing

permanent damage. Functionality at or exceeding the values listed is not implied. Exposure to these values for extended

periods may affect device reliability.

Recommended Operating Conditions

Package Pin Descriptions

Figure 4: Pin Diagram

5

±

VDDA

DATAIN+

DATAIN-

VSSA

LOCKDET

STS12

REFCLK

LOCKREFN

VSS

VDD

VDDA

VSSA

CAP+

CAP-

BYPASS

SD

DATAOUT+

DATAOUT-

CLKOUT+

CLKOUT-

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11