CS8412 datasheet(30/38 Pages) CIRRUS

30 / 38 page

CS8411 CS8412

DS61F1

FSYNC - Frame Sync, PIN 11.

Delineates the serial data and may indicate the particular channel, left or right, and may be an

input or output. The format is based on M0, M1, M2, and M3 pins.

SDATA - Serial Data, PIN 26.

Audio data serial output pin.

M0, M1, M2, M3 - Serial Port Mode Select, PINS 23, 24, 18, 17.

Selects the format of FSYNC and the sample edge of SCK with respect to SDATA. M3 selects

between eight normal modes (M3 = 0), and six special modes (M3 = 1).

Control Pins

VERF - Validity + Error Flag, PIN 28.

A logical OR’ing of the validity bit from the received data and the error flag. May be used by

interpolation filters to interpolate through errors.

U - User Bit, PIN 14.

Received user bit serial output port. FSYNC may be used to latch this bit externally. (Except in

I2S modes when this pin is updated at the active edge of FSYNC.)

C - Channel Status Output, PIN 1.

Received channel status bit serial output port. FSYNC may be used to latch this bit externally.

(Except in I2S modes when this pin is updated at the active edge of FSYNC.)

CBL - Channel Status Block Start, PIN 15.

The channel status block output is high for the first four bytes of channel status and low for the

last 20 bytes.

SEL - Select, PIN 16.

Control pin that selects either channel status information (SEL = 1) or error and frequency

information (SEL = 0) to be displayed on six of the following pins.

C0, Ca, Cb, Cc, Cd, Ce - Channel Status Output Bits, PINS 2-6, 27.

These pins are dual function with the ’C’ bits selected when SEL is high. Channel status

information is displayed for the channel selected by CS12. C0, which is channel status bit 0,

defines professional (C0 = 0) or consumer (C0 = 1) mode and further controls the definition of

the Ca-Ce pins. These pins are updated with the rising edge of CBL.

CS12 - Channel Select, PIN 13.

This pin is also dual function and is selected by bringing SEL high. CS12 selects sub-frame1

(when low) or sub-frame2 (when high) to be displayed by channel status pins C0 and Ca

through Ce.

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