XRT8001IP datasheet(25/48 Pages) EXAR

25 / 48 page

XRT8001

Rev. 1.01

XRT8001

WAN Clock

XRT8001

WAN Clock

FIN

CLK1

CLK2

P x 56kHz

P x 64kHz

Where: 1 < P < 32

1.544MHz

2.048MHz

1.544MHz

2.048MHz

6.3 Configuring the XRT8001 WAN Clock into the

“Fractional T1/E1 Reverse/Master” Mode

The user can configure the XRT8001 WAN Clock to

operate in the “Fractional T1/E1 Reverse/Master”

Mode by executing the following steps.

Figure 15. Illustration of the XRT8001 WAN Clock

Operating in the “Fractional T1/E1 Reverse/Master” Mode

Input

Frequency

PLL1 Output

Frequency

PLL2 Output

Frequency

Value to Write to

D4 – D1 in CR0

P x 56kHz

1.544MHz

2.048MHz

1001

P x 56kHz

1.544MHz

1010

P x 64kHz

2.048MHz

1.544MHz

1011

P x 64kHz

2.048MHz

1100

Step 1 – Configure the XRT8001 to operate in the

“MASTER” Mode, by pulling the “MSB” input pin (pin 8)

to VDD.

Step 2 – Review Table 6, and determine which combi-

nation of “Input Frequency” and “Output Frequencies”

(via PLL1 and PLL2) correlate with the desired configu-

ration.

Table 6. Listing of “Input Frequency” and “Output Frequency” Cases for “Fractional T1/E1 Reverse/

Master” Mode Operation

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