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8P34S2108NLGI 데이터시트(PDF) 7 Page - Integrated Device Technology

부품명 8P34S2108NLGI
상세설명  Dual 1:8 LVDS Output 1.8V Fanout Buffer
PDF  20 Pages
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제조업체  IDT [Integrated Device Technology]
홈페이지  http://www.idt.com
Logo IDT - Integrated Device Technology

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©2016 Integrated Device Technology, Inc.
October 20, 2016
8P34S2108 Datasheet
AC Electrical Characteristics
Table 10. AC Electrical Characteristics, VDDA = VDDB = VDDQA = VDDQB 1.8V ± 5%, TA = -40°C to 85°C [a]
[a]
Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal
equilibrium has been reached under these conditions.
Symbol
Parameter
Test Conditions
Minimum Typical
Maximum
Units
fREF
Input frequency
2GHz
V/t
Input edge rate
1.5
V/ns
tPD
Propagation delay[b], [c]
[b]
Measured from the differential input crossing point to the differential output crossing point.
[c]
Input VPP = 400mV.
CLKA to any QAx, CLKB to any nQBx
100
255
400
ps
tsk(o)
Output skew[d], [e]
20
40
ps
tsk(b)
Output bank skew[e], [f]
10
25
ps
tsk(p)
Pulse skew[g]
fREF = 100MHz
5
25
ps
tsk(pp)
Part-to-part skew[e], [h]
200
ps
tJIT
Buffer Additive Phase
Jitter, RMS;
500mV amplitude;
refer to Additive Phase
Jitter
fREF = 156.25MHz;
Integration range: 1kHz – 40MHz
60
80
fs
fREF = 156.25MHz square wave, VPP = 1V;
Integration range: 12kHz – 20MHz
45
60
fs
N(30M) Clock single-side band
phase noise
30MHz offset from carrier and noise floor
< -160
dBc/Hz
tJIT, SP
Spurious suppression,
coupling between
channels
fQA = 491.52MHz, fQB = 61.44MHz;
measured between neighboring outputs
-59
dB
fQA = 491.52MHz, fQB = 15.36MHz;
measured between neighboring outputs
-59
dB
tR / tF
Output rise/ fall time
10% to 90%, outputs loaded with 100
150
400
ps
20% to 80%, outputs loaded with 100
90
160
ps
VPP
Input voltage
amplitude
CLKA,
CLKB
0.15
1.2
V
VPP_DIFF
Differential
input voltage
amplitude
CLKA,
CLKB
0.3
2.4
V
VCMR
Common mode
input voltage[i]
1.1
VDD[j] – (VPP/2)V
VOD
Differential
output voltage
SELAA, SELAB = 0,
outputs loaded with 100
247
350
454
mV
SELAA, SELAB = 1,
outputs loaded with 100
350
500
650
mV
VOS
Offset voltage
SELAA, SELAB = 0
0.8
V
SELAA, SELAB = 1
0.7
V



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