STM32F401CBU6 datasheet(18/135 Pages) STMICROELECTRONICS

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STM32F401xB STM32F401xC

Functional overview

3.11

Clocks and startup

On reset the 16 MHz internal RC oscillator is selected as the default CPU clock. The

16 MHz internal RC oscillator is factory-trimmed to offer 1% accuracy at 25 °C. The

application can then select as system clock either the RC oscillator or an external 4-26 MHz

clock source. This clock can be monitored for failure. If a failure is detected, the system

automatically switches back to the internal RC oscillator and a software interrupt is

generated (if enabled). This clock source is input to a PLL thus allowing to increase the

frequency up to 84 MHz. Similarly, full interrupt management of the PLL clock entry is

available when necessary (for example if an indirectly used external oscillator fails).

Several prescalers allow the configuration of the two AHB buses, the high-speed APB

(APB2) and the low-speed APB (APB1) domains. The maximum frequency of the two AHB

buses is 84 MHz while the maximum frequency of the high-speed APB domains is 84 MHz.

The maximum allowed frequency of the low-speed APB domain is 42 MHz.

The devices embed a dedicated PLL (PLLI2S) which allows to achieve audio class

performance. In this case, the I2S master clock can generate all standard sampling

frequencies from 8 kHz to 192 kHz.

3.12

Boot modes

At startup, boot pins are used to select one out of three boot options:

•

Boot from user Flash

•

Boot from system memory

•

Boot from embedded SRAM

The bootloader is located in system memory. It is used to reprogram the Flash memory by

using either USART1(PA9/10), USART2(PD5/6), USB OTG FS in device mode (PA11/12)

through DFU (device firmware upgrade), I2C1(PB6/7), I2C2(PB10/3), I2C3(PA8/PB4),

SPI1(PA4/5/6/7), SPI2(PB12/13/14/15) or SPI3(PA15, PC10/11/12).

For more detailed information on the bootloader, refer to Application Note: AN2606,

STM32™ microcontroller system memory boot mode.

3.13

Power supply schemes

•

VDD = 1.7 to 3.6 V: external power supply for I/Os with the internal supervisor

(POR/PDR) disabled, provided externally through VDD pins. Requires the use of an

external power supply supervisor connected to the VDD and PDR_ON pins.

•

VDD = 1.8 to 3.6 V: external power supply for I/Os and the internal regulator (when

enabled), provided externally through VDD pins.

•

VSSA, VDDA = 1.7 to 3.6 V: external analog power supplies for ADC, Reset blocks, RCs

and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively, with

decoupling technique.

•

VBAT = 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and

backup registers (through power switch) when VDD is not present.

Refer to Figure 18: Power supply scheme for more details.

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