AS4SD32M16 datasheet(9/52 Pages) MICROSS

9 / 52 page

SDRAM

AS4SD32M16

Rev. 2.0 10/13

Micross Components reserves the right to change products or speciﬁcations without notice.

OPERATION

BANK/ROW ACTIVATION

Before any READ or WRITE commands can be issued to a

bank within the SDRAM, a row in that bank must be “opened.”

This is accomplished via the ACTIVE command, which selects

both the bank and the row to be activated (see Figure 3).

After opening a row (issuing an ACTIVE command), a

READ or WRITE command may be issued to that row, sub-

ject to the t

RCD speciﬁcation. tRCD (MIN) should be divided

by the clock period and rounded up to the next whole number

to determine the earliest clock edge after the ACTIVE com-

mand on which a READ or WRITE command can be entered.

For example, a tRCD speciﬁcation of 20ns with a 125 MHz

clock (8ns period) results in 2.5 clocks, rounded to 3. This is

reﬂected in Figure 4, which covers any case where 2 < t

RCD

(MIN)/

CK < 3. (The same procedure is used to convert

other speciﬁcation limits from time units to clock cycles.)

A subsequent ACTIVE command to a different row in the

same bank can only be issued after the previous active row

has been “closed” (precharged). The minimum time interval

between successive ACTIVE commands to the same bank is

deﬁned by t

RC.

A subsequent ACTIVE command to another bank can be

issued while the ﬁrst bank is being accessed, which results in

a reduction of total row-access overhead. The minimum time

interval between successive ACTIVE commands to different

banks is deﬁned by t

RRD.

FIGURE 3: Activating a Speciﬁc Row

in a Speciﬁc Bank

FIGURE 4: Example - Meeting t

RCD

(MIN) When 2 < t

RCD

(MIN)/ t

< 3

AS4SD32M16 데이터시트(PDF) 9 Page - Micross Components

AS4SD32M16 데이터시트(HTML) 9 Page - Micross Components

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52

데이터시트 다운로드

링크 URL