SAP5SD-A-G1-R datasheet(31/66 Pages) IDT

31 / 66 page

SAP51 / SAP5S Datasheet

January 28, 2016

The availability of new parameter output data is signaled by the Parameter Strobe (PSTBn) signal as shown in

Figure 5.2.

In addition to the basic I/O function, the first parameter output event after an SAP5 reset has an additional effect.

It enables the data exchange functionality.

Any SAP5 reset sets the Parameter Output Register to FHEX and forces the parameter output drivers to the high

impedance state. Simultaneously, a Parameter Strobe is generated with the same tsetup timing and tPSTBn pulse

width as would be used to drive new output data.

Table 5.9

Timing for Parameter Ports

PARAMETER

SYMBOL

CONDITIONS

MIN

MAX

UNIT

Output data is valid after PSTBn high-low edge

tSTB

0.0

1.5

µs

Pulse width of Parameter Strobe (PSTBn)

tPSTBn

6.0

6.8

µs

Acceptance of input data

tPI-latch

10.5

12.5

µs

Parameter Port is at high impedance state after PSTBn

high-low edge

tP-off

56.0

64.5

µs

The timing of the resulting voltage signal also depends on the external pull up resistor.

The parameter input data must be stable within the period defined by min. and max. values of tPI-latch.

Concerns the IO configuration “7” only (see Table 5.14).

Figure 5.2

Timing Diagram for Parameter Port P[3:0], PSTBn

PSTBn

Parameter port output data

Parameter input value (PIx) = Parameter output value (POx) (wired AND with external signal

source value)

Keep stable

min

max

P[3:0]

tPI-latch

tPSTBn

tP-off

tSTB

SAP5SD-A-G1-R 데이터시트(PDF) 31 Page - Integrated Device Technology

SAP5SD-A-G1-R 데이터시트(HTML) 31 Page - Integrated Device Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66

데이터시트 다운로드

링크 URL