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SAP5SD-A-G1-R 데이터시트(PDF) 43 Page - Integrated Device Technology

부품명 SAP5SD-A-G1-R
상세설명  AS-Interface Spec. V3.0 Compliant Universal AS-i IC
PDF  66 Pages
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제조업체  IDT [Integrated Device Technology]
홈페이지  http://www.idt.com
Logo IDT - Integrated Device Technology

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SAP51 / SAP5S Datasheet
© 2016 Integrated Device Technology, Inc.
43
January 28, 2016
5.13.2. Logic Controlled Reset
The SAP5 also becomes reset after reception of Reset_Slave or Broadcast_Reset commands, expiration of the
(enabled) Communication Watchdog, or entering a prohibited state machine state (i.e., due to heavy EMI).
5.13.3. External Reset
The SAP5 can be reset externally by pulling the DSTBn pin LOW for more than the minimum reset time. The
external reset input function is provided in every operational mode of the SAP5: Slave Mode and Master/Repeater
Mode. The signal timings are given in Table 5.20.
Table 5.20 Timing of External Reset
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNIT
DSTBn low time for no reset initiation
tnoRESET
90
ms
Reset execution time:
DSTBn H/L transition to Hi-Z output drives at DO[3:0], P[3:0]
tRESET
99
ms
State Machine initialization time after reset (EEPROM read out)
tINIT
2
ms
Figure 5.6
Timing Diagram External Reset via DSTBn
DSTBn
D[3:0]
tnoRESET
P[3:0]
Hi-Z
Data port output data
Parameter port output data
External Reset
tRESET
Hi-Z
tINIT
The external reset is generated as “edge sensitive” to the expiration of the tRESET timer. The initialization
procedure is starting immediately after the event, independent of the state of DSTBn. The external reset state
persists if DSTBn still remains low after tRESET + tINIT. The corresponding error state display is described in section
5.11.
5.14. UART
The UART performs a syntactical and timing analysis of the telegrams received at the AS-i input channel. It
converts the pulse-coded AS-i input signal into a Manchester-II-coded bit stream and provides the receive register
with decoded telegram bits. The UART also realizes the Manchester-II-coding of a slave answer.



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