LAN89730 datasheet(176/218 Pages) MICROCHIP

176 / 218 page

LAN89730

DS60001348A-page 176

 2013-2015 Microchip Technology Inc.

6.4.13

CHECKSUM OFFLOAD ENGINE CONTROL REGISTER (COE_CR)

This register controls the RX and TX checksum offload engines.

Address:

130h

Size:

32 bits

Bits

Description

Type

Default

31:17

RESERVED

TX Checksum Offload Engine Enable (TX_COE_EN)

TX_COE_EN may only be changed if the TX path is disabled. If it is desired to

change this value during run time, it is safe to do so only after the MAC is dis-

abled and the TLI is empty.

0 = The TXCOE is bypassed.

1 = The TXCOE is enabled.

R/W

15:2

RESERVED

RX Checksum Offload Engine Mode (RX_COE_MODE)

This register indicates whether the COE will check for VLAN tags or a SNAP

header prior to beginning its checksum calculation. In its default mode, the

calculation will always begin 14 bytes into the frame.

RX_COE_MODE may only be changed if the RX path is disabled. If it is

desired to change this value during run time, it is safe to do so only after the

MAC is disabled and the TLI is empty.

0 = Begin checksum calculation after first 14 bytes of Ethernet Frame.

1 = Begin checksum calculation at start of L3 packet by adjusting for VLAN

tags and/or SNAP header.

R/W

RX Checksum Offload Engine Enable (RX_COE_EN)

RX_COE_EN may only be changed if the RX path is disabled. If it is desired

to change this value during run time, it is safe to do so only after the MAC is

disabled and the TLI is empty.

0 = The RXCOE is bypassed.

1 = The RXCOE is enabled.

R/W

LAN89730 데이터시트(PDF) 176 Page - Microchip Technology

LAN89730 데이터시트(HTML) 176 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL